公开(公告)号：US20190109196A1

公开(公告)日：2019-04-11

申请号：US16211891

申请日：2018-12-06

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Takeshi SONEHARA ,  Erika KODAMA ,  Nobutaka NAKAMURA ,  Tsuneo INABA ,  Koichi NAKAYAMA

IPC: H01L29/417 ,  H01L27/11556 ,  H01L27/1158 ,  H01L23/528

Abstract: According to one embodiment, a semiconductor memory device includes a plurality of electrodes, extending in a first direction and a second direction orthogonal to the first direction are stacked one over the other, and include opposed sides extending in the second direction, a plurality of protrusion portions extending from the first side of the electrodes and spaced from one another in the second direction, and an extraction portion extending from the second side of the electrode. First and second contact plugs extend in a third direction orthogonal to the first and second directions, one of each contacting one of the extraction portions, wherein the extraction portion extending from the uppermost of the electrodes is located closer to the center of the second side in the second direction, than the location of the extraction portion extending from the lowermost of the electrodes.

公开(公告)号：US20190006384A1

公开(公告)日：2019-01-03

申请号：US15909432

申请日：2018-03-01

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Taichi IWASAKI ,  Takeshi SONEHARA ,  Hiroyuki NITTA

IPC: H01L27/11582 ,  H01L23/58 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/11573 ,  H01L23/00

CPC classification number: H01L27/11582 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/26513 ,  H01L21/31053 ,  H01L21/31116 ,  H01L21/32053 ,  H01L21/32055 ,  H01L21/3212 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76846 ,  H01L21/78 ,  H01L23/562 ,  H01L23/564 ,  H01L23/585 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/1037 ,  H01L29/7883 ,  H01L29/7889 ,  H01L29/7926

Abstract: A semiconductor memory device includes a semiconductor layer having a termination region surrounding a device region, the termination region including a first stacked body having a first, insulating, layer located on a surface of the substrate, a second, conductive, layer located over the first layer, and a third, insulating, layer located over the second layer, an opening extending through the first stacked body, a fourth, insulating, layer located in the opening in the first stacked body and over the surface of the semiconductor substrate in the opening, a fifth, insulating, layer, located over the fourth layer, and a wall surrounding the device region, the wall extending inwardly of the opening and contacting one of the surface of the semiconductor substrate or a nitride material on the surface of the substrate, wherein the composition of the third and fifth layers is different from that of the first and third layers.

公开(公告)号：US20210202263A1

公开(公告)日：2021-07-01

申请号：US17183599

申请日：2021-02-24

Applicant: Toshiba Memory Corporation

Inventor： Takeshi SONEHARA ,  Takahiro HIRAI ,  Masaaki HIGUCHI ,  Takashi SHIMIZU

IPC: H01L21/321 ,  H01L27/11582

Abstract: According to an embodiment, a nonvolatile semiconductor memory device comprises a plurality of conductive layers that are stacked in plurality in a first direction via an inter-layer insulating layer, that extend in a second direction which intersects the first direction, and that are disposed in plurality in a third direction which intersects the first direction and the second direction. In addition, the same nonvolatile semiconductor memory device comprises: a semiconductor layer that has the first direction as a longitudinal direction; a tunnel insulating layer that contacts a side surface of the semiconductor layer; a charge accumulation layer that contacts a side surface of the tunnel insulating layer; and a block insulating layer that contacts a side surface of the charge accumulation layer. Furthermore, in the same nonvolatile semiconductor memory device, an end in the third direction of the plurality of conductive layers is rounded.

公开(公告)号：US20190139782A1

公开(公告)日：2019-05-09

申请号：US16235435

申请日：2018-12-28

Applicant: Toshiba Memory Corporation

Inventor： Takeshi SONEHARA ,  Takahiro HIRAI ,  Masaaki HIGUCHI ,  Takashi SHIMIZU

IPC: H01L21/321 ,  H01L27/11582

Abstract: According to an embodiment, a nonvolatile semiconductor memory device comprises a plurality of conductive layers that are stacked in plurality in a first direction via an inter-layer insulating layer, that extend in a second direction which intersects the first direction, and that are disposed in plurality in a third direction which intersects the first direction and the second direction. In addition, the same nonvolatile semiconductor memory device comprises: a semiconductor layer that has the first direction as a longitudinal direction; a tunnel insulating layer that contacts a side surface of the semiconductor layer; a charge accumulation layer that contacts a side surface of the tunnel insulating layer; and a block insulating layer that contacts a side surface of the charge accumulation layer. Furthermore, in the same nonvolatile semiconductor memory device, an end in the third direction of the plurality of conductive layers is rounded.

公开(公告)号：US20180269228A1

公开(公告)日：2018-09-20

申请号：US15980966

申请日：2018-05-16

Applicant: Toshiba Memory Corporation

Inventor： Takeshi SONEHARA ,  Masaru KITO

IPC: H01L27/11582 ,  H01L27/11575 ,  H01L27/11565 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575

Abstract: According to an embodiment, a semiconductor memory device comprises control gate electrodes and a semiconductor layer. The control gate electrodes are stacked above a substrate. The semiconductor layer has as its longitudinal direction a direction perpendicular to the substrate. The semiconductor memory device further comprises first and second control gate electrodes and third and fourth control gate electrodes stacked sequentially above the substrate and first through fourth via contacts connected to these first through fourth control gate electrodes. The third and fourth control gate electrodes face the first and second control gate electrodes. Positions of the first and second via contacts are far from each other. Positions of the third and fourth via contacts are close to each other.

公开(公告)号：US20180226422A1

公开(公告)日：2018-08-09

申请号：US15461598

申请日：2017-03-17

Applicant: Toshiba Memory Corporation

Inventor： Takeshi SONEHARA

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L27/11524

CPC classification number: H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: A semiconductor memory device according to an embodiment includes a stacked body in which an electrode film and an insulating film are alternately stacked along a first direction, a semiconductor member extending in the first direction and piercing the stacked body, and a charge storage member provided between the semiconductor member and the electrode film. The electrode film includes a first portion. The first portion is composed of a metal silicide. The first portion surrounds the semiconductor member as viewed from the first direction.