公开(公告)号：US20180068739A1

公开(公告)日：2018-03-08

申请号：US15459261

申请日：2017-03-15

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Yasuhiro SHIINO ,  Tomoaki NAKANO ,  Shigefumi IRIEDA ,  Masashi YOSHIDA

IPC: G11C16/34 ,  G11C16/10

CPC classification number: G11C16/3459 ,  G11C11/5628 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/10

Abstract: According to one embodiment, a memory device includes a plurality of memory cells; and a first word line connected to the memory cells. When data is written, a first program voltage is applied to the first word line, a first verify voltage is applied to the first word line to obtain a first verify result, a second program voltage is applied to the first word line, a second verify voltage is applied to the first word line to obtain a second verify result, and among the memory cells, a first memory cell whose first verify result is a pass is set to a program inhibited state when the second program voltage is applied and set as a target of the detection of the second verify result.