公开(公告)号：US20180068739A1

公开(公告)日：2018-03-08

申请号：US15459261

申请日：2017-03-15

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Yasuhiro SHIINO ,  Tomoaki NAKANO ,  Shigefumi IRIEDA ,  Masashi YOSHIDA

IPC: G11C16/34 ,  G11C16/10

CPC classification number: G11C16/3459 ,  G11C11/5628 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/10

Abstract: According to one embodiment, a memory device includes a plurality of memory cells; and a first word line connected to the memory cells. When data is written, a first program voltage is applied to the first word line, a first verify voltage is applied to the first word line to obtain a first verify result, a second program voltage is applied to the first word line, a second verify voltage is applied to the first word line to obtain a second verify result, and among the memory cells, a first memory cell whose first verify result is a pass is set to a program inhibited state when the second program voltage is applied and set as a target of the detection of the second verify result.

公开(公告)号：US20210225449A1

公开(公告)日：2021-07-22

申请号：US17223202

申请日：2021-04-06

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Yuki SAKAGUCHI ,  Tatsuo IZUMI ,  Masashi YOSHIDA

IPC: G11C16/14 ,  G11C16/04 ,  G11C16/32 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11524 ,  H01L27/11519

Abstract: A semiconductor memory device includes a first wiring, a first memory transistor connected to the first wiring, a first transistor connected between the first wiring and the first memory transistor, a second transistor connected between the first wiring and the first transistor, and second to fourth wirings respectively connected to gate electrodes of the first memory transistor, the first transistor, and the second transistor. From a first timing to a second timing, a voltage difference between the first wiring and the third wiring is maintained at a predetermined value, a voltage difference between the third wiring and the fourth wiring is maintained at a predetermined value, a voltage of the first wiring becomes larger than a voltage of the third wiring, and the voltage of the third wiring becomes larger than a voltage of the fourth wiring.

公开(公告)号：US20200082893A1

公开(公告)日：2020-03-12

申请号：US16688368

申请日：2019-11-19

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Yuichiro SUZUKI ,  Noboru OOIKE ,  Masashi YOSHIDA

IPC: G11C16/34 ,  G11C16/26 ,  G11C16/10 ,  G11C16/08 ,  G11C16/04

Abstract: According to one embodiment, a semiconductor storage device includes: a NAND string with a first set of memory cells including a first memory cell; and a second set of memory cells including a second memory cell disposed above the first memory cell. The number of memory cells included in the first set is different from that of memory cells included in the second set. During a program verify operation when a data item of a level is written to a memory cell of the first set and a memory cell of the second set, a first verify voltage is applied to the gate of the memory cell of the first set and a second verify voltage different from the first verify voltage is applied to the gate of the memory cell of the second set.