公开(公告)号：US20220075686A1

公开(公告)日：2022-03-10

申请号：US17530748

申请日：2021-11-19

申请人： TOSHIBA MEMORY CORPORATION

发明人： Yuta KUMANO ,  Hironori UCHIKAWA ,  Kosuke MORINAGA ,  Naoaki KOKUBUN ,  Masahiro KIYOOKA ,  Yoshiki NOTANI ,  Kenji SAKURADA ,  Daiki WATANABE

IPC分类号： G06F11/10 ,  G11C11/56 ,  H03M13/00 ,  H03M13/37 ,  G11C29/52

摘要： According to one embodiment, a memory system includes a non-volatile memory, a memory interface that reads data recorded in the non-volatile memory as a received value, a converting unit that converts the received value to first likelihood information by using a first conversion table, a decoder that decodes the first likelihood information, a control unit that outputs an estimated value with respect to the received value, which is a decoding result obtained by the decoding, when decoding by the decoder has succeeded, and a generating unit that generates a second conversion table based on a decoding result obtained by the decoding, when decoding of the first likelihood information by the decoder has failed. When the generating unit generates the second conversion table, the converting unit converts the received value to the second likelihood information by using the second conversion table, and the decoder decodes the second likelihood information.

公开(公告)号：US20190089384A1

公开(公告)日：2019-03-21

申请号：US15909589

申请日：2018-03-01

申请人： TOSHIBA MEMORY CORPORATION

发明人： Yuta KUMANO ,  Kazumasa YAMAMOTO ,  Hironori UCHIKAWA ,  Akira YAMAGA

IPC分类号： H03M13/37 ,  H03M13/15 ,  H03M13/11 ,  H03M13/29 ,  G06F11/10

摘要： A memory system includes a nonvolatile memory and a memory controller configured to perform reading of a concatenation code from the nonvolatile memory in response to an external command, the memory controller including a decoder circuit which decodes a reception word in the concatenation code. The decoder circuit includes a first external code decoder that performs decoding on an external code portion, an internal code in-error bit estimation unit that performs estimation of an in-error bit on a bit sequence from the first external code decoder, based on a rule for an internal code in the concatenation code, and outputs a set of in-error bits that is obtained by the estimation, and a second external code decoder that performs decoding which uses the set of in-error bits that is output from the internal code in-error bit estimation unit, on the bit sequence from the first external code decoder.

公开(公告)号：US20190089377A1

公开(公告)日：2019-03-21

申请号：US15919788

申请日：2018-03-13

申请人： Toshiba Memory Corporation

发明人： Yuta KUMANO ,  Yoshiyuki Sakamaki ,  Hironori Uchikawa

IPC分类号： H03M13/11 ,  H03M13/25 ,  G06F11/10 ,  H03M13/15 ,  G06F17/16

CPC分类号： H03M13/1171 ,  G06F11/1068 ,  G06F17/16 ,  H03M13/1174 ,  H03M13/1182 ,  H03M13/152 ,  H03M13/255 ,  H03M13/611

摘要： According to one embodiment, a memory system comprises an encoder that encodes by a graph code and a data holding unit that holds data to be used in encoding. A check matrix of the graph code includes first to sixth submatrices, and the encoder produces a first vector obtained by multiplying an information word and the first submatrix, produces a second vector obtained by multiplying the information word and the third submatrix, produces a third vector obtained by multiplying the first vector and the fifth submatrix inverted in sign, produces a fourth vector obtained by adding the third vector and the second vector, produces a first parity obtained by multiplying the fourth vector and the data, produces a fifth vector obtained by multiplying the first parity and the second submatrix inverted in sign, and produces a second parity obtained by adding the fifth vector and the first vector.