公开(公告)号：US20130203232A1

公开(公告)日：2013-08-08

申请号：US13426832

申请日：2012-03-22

申请人： TZUNG-HAN LEE ,  CHUNG-LIN HUANG ,  RON-FU CHU

发明人： TZUNG-HAN LEE ,  CHUNG-LIN HUANG ,  RON-FU CHU

IPC分类号： H01L21/768

CPC分类号： H01L27/10894 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10885

摘要： A manufacturing method of a random access memory includes the following steps: providing a semiconductor structure having an array region and a peripheral region; forming a plurality of first trenches in the array region, and concurrently, a plurality of second trenches on the peripheral region; forming a polysilicon layer to cover the array region and the peripheral region, and the first and the second trenches are filled up with the polysilicon layer; planarizing the polysilicon layer so the remaining polysilicon layer only resides in the first and the second trenches; forming a conductive layer on the semiconductor structure; patterning the conductive layer to form a plurality of landing pads on the array region, and a plurality of bit line units on the peripheral region; and forming a plurality of capacitor units which is in electrical connection to the landing pads.

摘要翻译： 随机存取存储器的制造方法包括以下步骤：提供具有阵列区域和周边区域的半导体结构; 在阵列区域中形成多个第一沟槽，同时在周边区域上形成多个第二沟槽; 形成多晶硅层以覆盖阵列区域和外围区域，并且第一和第二沟槽被多晶硅层填充; 平坦化多晶硅层，使得剩余的多晶硅层仅驻留在第一和第二沟槽中; 在半导体结构上形成导电层; 图案化导电层以在阵列区域上形成多个着陆焊盘，以及在周边区域上形成多个位线单元; 以及形成与所述着陆焊盘电连接的多个电容器单元。

公开(公告)号：US20130168801A1

公开(公告)日：2013-07-04

申请号：US13421996

申请日：2012-03-16

申请人： TZUNG-HAN LEE ,  CHUNG-LIN HUANG ,  RON FU CHU

发明人： TZUNG-HAN LEE ,  CHUNG-LIN HUANG ,  RON FU CHU

IPC分类号： H01L29/06 ,  H01L21/762

CPC分类号： H01L21/76224

摘要： The instant disclosure relates to a method of forming an isolation area. The method includes the steps of: providing a substrate having a first type of ion dopants, where the substrate has a plurality of trenches formed on the cell areas and the isolation area between the cell areas of the substrate, with the side walls of the trenches having an oxidation layer formed thereon and the trenches are filled with a metallic structure; removing the metallic structure from the trenches of the isolation area; implanting a second type of ions into the substrate under the trenches of the isolation area; and filling all the trenches with an insulating structure, where the trenches of the isolation area are filled up fully by the insulating structure to form a non-metallic isolation area.

摘要翻译： 本公开涉及形成隔离区域的方法。 该方法包括以下步骤：提供具有第一类型的离子掺杂剂的衬底，其中衬底具有形成在单元区域上的多个沟槽和衬底的单元区域之间的隔离区域与沟槽的侧壁 其上形成有氧化层，并且沟槽填充有金属结构; 从隔离区的沟槽移除金属结构; 在隔离区的沟槽下方将第二类型的离子注入到衬底中; 并用绝缘结构填充所有沟槽，其中隔离区域的沟槽由绝缘结构完全填充以形成非金属隔离区域。

公开(公告)号：US20110092044A1

公开(公告)日：2011-04-21

申请号：US12699399

申请日：2010-02-03

申请人： SHIN-BIN HUANG ,  TZUNG-HAN LEE ,  CHUNG-LIN HUANG

发明人： SHIN-BIN HUANG ,  TZUNG-HAN LEE ,  CHUNG-LIN HUANG

IPC分类号： H01L21/02

CPC分类号： H01L28/92

摘要： A method for manufacturing capacitor lower electrodes includes a dielectric layer, a first silicon nitride layer and a hard mask layer; partially etching the hard mask layer, the first silicon nitride layer and the dielectric layer to form a plurality of concave portions; depositing a second silicon nitride layer onto the hard mask layer and into the concave portions; partially etching the second silicon nitride layer, the hard mask layer and the dielectric layer to form a plurality of trenches; forming a capacitor lower electrode within each trench and partially etching the first silicon nitride layer, the second silicon nitride layer, the dielectric layer and the capacitor lower electrodes to form an etching area; and etching and removing the dielectric layer from the etching area, thereby a periphery of each capacitor lower electrode is surrounded and attached to by the second silicon nitride layer.

摘要翻译： 制造电容器下电极的方法包括电介质层，第一氮化硅层和硬掩模层; 部分地蚀刻硬掩模层，第一氮化硅层和电介质层以形成多个凹部; 在所述硬掩模层上沉积第二氮化硅层并进入所述凹部; 部分蚀刻第二氮化硅层，硬掩模层和电介质层以形成多个沟槽; 在每个沟槽内形成电容器下电极，并部分地蚀刻第一氮化硅层，第二氮化硅层，电介质层和电容器下电极以形成蚀刻区域; 并且从蚀刻区域蚀刻除去电介质层，由此每个电容器下电极的周围被第二氮化硅层包围并附着。

公开(公告)号：US20130059442A1

公开(公告)日：2013-03-07

申请号：US13282593

申请日：2011-10-27

申请人： TZUNG-HAN LEE ,  CHUNG-LIN HUANG

发明人： TZUNG-HAN LEE ,  CHUNG-LIN HUANG

IPC分类号： H01L21/302

CPC分类号： H01L21/3065 ,  H01L21/3081 ,  H01L21/3083

摘要： A method for adjusting the trench depth of a substrate has the steps as follows. Forming a patterned covering layer on the substrate, wherein the patterned covering layer defines a wider spacing and a narrower spacing. Forming a wider buffering layer arranged in the wider spacing and a narrower buffering layer arranged in the narrower spacing. The thickness of the narrower buffering layer is thinner than the wider buffering layer. Implementing dry etching process to make the substrate corresponding to the wider and the narrower buffering layers form a plurality of trenches. When etching the wider and the narrower buffering layers, the narrower buffering layer is removed firstly, so that the substrate corresponding to the narrower buffering layer will be etched early than the substrate corresponding to the wider buffering layer.

摘要翻译： 用于调整衬底的沟槽深度的方法具有以下步骤。 在衬底上形成图案化的覆盖层，其中图案化覆盖层限定更宽的间隔和更窄的间隔。 形成更宽的间隔布置的较宽的缓冲层和以较窄的间隔布置的较窄的缓冲层。 较窄的缓冲层的厚度比较宽的缓冲层薄。 实施干蚀刻工艺以使与较宽和较窄缓冲层相对应的衬底形成多个沟槽。 当蚀刻较宽和较窄的缓冲层时，首先去除较窄的缓冲层，使得对应于较窄缓冲层的衬底将比对应于较宽缓冲层的衬底早蚀刻。

公开(公告)号：US20130168812A1

公开(公告)日：2013-07-04

申请号：US13426848

申请日：2012-03-22

申请人： TZUNG-HAN LEE ,  CHUNG-LIN HUANG ,  RON-FU CHU

发明人： TZUNG-HAN LEE ,  CHUNG-LIN HUANG ,  RON-FU CHU

IPC分类号： H01L29/92 ,  H01L21/02

CPC分类号： H01L28/91 ,  H01L27/10852

摘要： A manufacturing method for memory capacitor having a robust moat, comprising the steps of: providing a substrate; forming a patterned sacrificial layer on the substrate having a moat to separate a cell area and a peripheral area; forming a supporting layer on the sacrificial layer and filling the moat to form a annular member, wherein the supporting layer and the sacrificial layer arranged in alignment to form a stack structure; forming a plurality row of capacitor trenches on the substrate, wherein the capacitor trenches are formed at intervals in the stack structure; and forming a conducting layer on the supporting layer and covering the substrate and the inner surface of the stack structure defining the capacitor trenches.

摘要翻译： 一种具有坚固的护城河的存储电容器的制造方法，包括以下步骤：提供衬底; 在具有护城河的基板上形成图案化的牺牲层以分离单元区域和周边区域; 在所述牺牲层上形成支撑层并填充所述护城河以形成环形构件，其中所述支撑层和所述牺牲层排列成对准以形成堆叠结构; 在所述基板上形成多排电容器沟槽，其中所述电容器沟槽在所述堆叠结构中间隔地形成; 以及在所述支撑层上形成导电层，并覆盖所述基板和限定所述电容器沟槽的所述堆叠结构的内表面。

公开(公告)号：US20130168751A1

公开(公告)日：2013-07-04

申请号：US13426825

申请日：2012-03-22

申请人： TZUNG-HAN LEE ,  CHUNG-LIN HUANG ,  RON FU CHU

发明人： TZUNG-HAN LEE ,  CHUNG-LIN HUANG ,  RON FU CHU

IPC分类号： H01L27/108

CPC分类号： H01L27/10873 ,  H01L27/10885 ,  H01L27/10891

摘要： The instant disclosure relates to a high-k metal gate random access memory. The memory includes a substrate, a plurality of bit line units, source regions, gate structures, drain regions, word line units, and capacitance units. The substrate has a plurality of trenches, and the bit line units are arranged on the substrate. The source regions are disposed on the bit line units, and the gate structures are disposed on the source regions. Each gate structure has a metal gate and a channel area formed therein. The gate structures are topped with the drain regions. The word lines units are arranged between the source and drain regions The capacitance units are disposed on the drain regions. Another memory is also disclosed, where each drain region and a portion of each gate structure are disposed in the respective capacitance unit, with the drain region being a lower electrode layer.

摘要翻译： 本公开涉及高k金属栅极随机存取存储器。 存储器包括衬底，多个位线单元，源极区，栅极结构，漏极区，字线单元和电容单元。 衬底具有多个沟槽，并且位线单元布置在衬底上。 源极区域设置在位线单元上，栅极结构设置在源极区域上。 每个栅极结构具有形成在其中的金属栅极和沟道区域。 栅极结构顶部带有漏极区域。 字线单元布置在源区和漏区之间。电容单元设置在漏区上。 还公开了另一种存储器，其中每个漏极区域和每个栅极结构的一部分设置在相应的电容单元中，漏极区域是下部电极层。

公开(公告)号：US20130203233A1

公开(公告)日：2013-08-08

申请号：US13461921

申请日：2012-05-02

申请人： TZUNG-HAN LEE ,  CHUNG-LIN HUANG ,  RON-FU CHU

发明人： TZUNG-HAN LEE ,  CHUNG-LIN HUANG ,  RON-FU CHU

IPC分类号： H01L21/02

CPC分类号： H01L28/91 ,  H01L27/10894

摘要： A manufacturing method of a memory capacitor without a moat structure includes the steps of: providing a semiconductor substrate defined with an array region and a peripheral region; forming a first oxidized layer on the array region; forming a second oxidized layer on the peripheral region; planarizing the first and the second oxidized layers; forming an insulating layer on the first and the second oxidized layers; forming a plurality of trenches on the array region, where the trenches pass through the first oxidized layer and the insulating layer on the first oxidized layer; forming a conductive layer on the side and base surfaces of each trench; removing a portion of the conductive layer and a portion of the insulating layer to form a plurality of notches to expose the first oxidized layer; and removing the first oxidized layers which are exposed from the notches.

摘要翻译： 具有槽护结构的存储电容器的制造方法包括以下步骤：提供限定有阵列区域和周边区域的半导体衬底; 在阵列区域上形成第一氧化层; 在周边区域形成第二氧化层; 平面化第一和第二氧化层; 在所述第一和第二氧化层上形成绝缘层; 在阵列区域上形成多个沟槽，其中沟槽穿过第一氧化层和第一氧化层上的绝缘层; 在每个沟槽的侧面和底面上形成导电层; 去除所述导电层的一部分和所述绝缘层的一部分以形成多个凹口以暴露所述第一氧化层; 以及去除从凹口露出的第一氧化层。

公开(公告)号：US20130168811A1

公开(公告)日：2013-07-04

申请号：US13417438

申请日：2012-03-12

申请人： TZUNG-HAN LEE ,  CHUNG-LIN HUANG ,  RON-FU CHU

发明人： TZUNG-HAN LEE ,  CHUNG-LIN HUANG ,  RON-FU CHU

IPC分类号： H01L29/92

CPC分类号： H01L27/1085 ,  H01L28/75 ,  H01L29/92 ,  H01L29/94

摘要： The instant disclosure relates to a capacitor having multi-layered electrodes. The capacitor includes a dielectric layer having a first surface and a second surface oppositely arranged, a first electrode formed on the first surface, and a second electrode formed on the second surface. At least one of the first and second electrodes having a low band gap material layer formed on the dielectric layer and a conducting layer formed on the low band gap material layer. The band gap of the low band gap material layer is lower than the band gap of the conducting layer.

摘要翻译： 本公开涉及具有多层电极的电容器。 电容器包括具有相对布置的第一表面和第二表面的介电层，形成在第一表面上的第一电极和形成在第二表面上的第二电极。 第一和第二电极中的至少一个具有形成在电介质层上的低带隙材料层和形成在低带隙材料层上的导电层。 低带隙材料层的带隙低于导电层的带隙。