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    Semiconductor memory device
    2.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5640363A

    公开(公告)日：1997-06-17

    申请号：US542958

    申请日：1995-10-13

    申请人： Kiyohiro Furutani ,  Tadaaki Yamauchi ,  Makiko Aoki

    发明人： Kiyohiro Furutani ,  Tadaaki Yamauchi ,  Makiko Aoki

    IPC分类号： G11C11/41 ,  G11C7/12 ,  G11C7/22 ,  G11C11/407 ,  G11C11/409 ,  G11C7/00

    CPC分类号： G11C7/12 ,  G11C7/22

    摘要： The present invention semiconductor memory device includes common signal lines from which memory cell data is read and an amplifier for detecting a potential difference between these common signal lines, wherein equalization of the common signal lines is started when a potential difference required for an operation of the amplifier is generated on the common signal lines.Also, a semiconductor memory device having a plurality of memory cell arrays includes first common signal lines for reading memory cell data and second common signal lines having the first common signal lines connected thereto. The first common signal lines are operated in an activated state only after a writing operation, whereby access time of the semiconductor device can be shortened.

    摘要翻译： 本发明的半导体存储器件包括从其读取存储单元数据的公共信号线和用于检测这些公共信号线之间的电位差的放大器，其中当所述公共信号线的操作所需的电位差 在公共信号线上产生放大器。 此外，具有多个存储单元阵列的半导体存储器件包括用于读取存储单元数据的第一公共信号线和与其连接的第一公共信号线的第二公共信号线。 第一公共信号线仅在写入操作之后才被激活，从而可以缩短半导体器件的访问时间。

    Semiconductor memory device having equalization signal generating circuit
    3.
    发明授权
    Semiconductor memory device having equalization signal generating circuit 失效
    具有均衡信号发生电路的半导体存储器件

    公开(公告)号：US5487043A

    公开(公告)日：1996-01-23

    申请号：US306098

    申请日：1994-09-14

    申请人： Kiyohiro Furutani ,  Tadaaki Yamauchi ,  Makiko Aoki

    发明人： Kiyohiro Furutani ,  Tadaaki Yamauchi ,  Makiko Aoki

    IPC分类号： G11C11/41 ,  G11C7/12 ,  G11C7/22 ,  G11C11/407 ,  G11C11/409 ,  G11C7/00

    CPC分类号： G11C7/12 ,  G11C7/22

    摘要： The present invention semiconductor memory device includes common signal lines from which memory cell data is read and an amplifier for detecting a potential difference between these common signal lines, wherein equalization of the common signal lines is started when a potential difference required for an operation of the amplifier is generated on the common signal lines. Also, a semiconductor memory device having a plurality of memory cell arrays includes first common signal lines for reading memory cell data and second common signal lines having the first common signal lines connected thereto. The first common signal lines are operated in an activated state only after a writing operation, whereby access time of the semiconductor device can be shortened.

    摘要翻译： 本发明的半导体存储器件包括从其读取存储单元数据的公共信号线和用于检测这些公共信号线之间的电位差的放大器，其中当所述公共信号线的操作所需的电位差 在公共信号线上产生放大器。 此外，具有多个存储单元阵列的半导体存储器件包括用于读取存储单元数据的第一公共信号线和与其连接的第一公共信号线的第二公共信号线。 第一公共信号线仅在写入操作之后才被激活，从而可以缩短半导体器件的访问时间。

    Semiconductor device with pump circuit
    6.
    发明授权
    Semiconductor device with pump circuit 有权
    带泵电路的半导体器件

    公开(公告)号：US07268612B2

    公开(公告)日：2007-09-11

    申请号：US11699427

    申请日：2007-01-30

    申请人： Minoru Senda ,  Kiyohiro Furutani ,  Taku Ogura ,  Shigehiro Kuge ,  Satoshi Kawasaki ,  Tadaaki Yamauchi

    发明人： Minoru Senda ,  Kiyohiro Furutani ,  Taku Ogura ,  Shigehiro Kuge ,  Satoshi Kawasaki ,  Tadaaki Yamauchi

    IPC分类号： G05F1/10

    CPC分类号： G11C16/30 ,  G11C5/145 ,  G11C16/04 ,  H02M3/073 ,  H02M2003/071 ,  H02M2003/075 ,  H02M2003/077 ,  H03K3/356113

    摘要： In the present semiconductor device a positive, driving pump circuit is driven by an external power supply potential EXVDD (for example of 1.8V) to generate a positive voltage VPC (for example of 2.4V). A negative pump circuit for internal operation is driven by the positive voltage VPC to generate a negative voltage VNA (for example of −9.2V) required in an erasure or similar internal operation for a word line. The negative pump circuit for internal operation can have a smaller number of stages of pump and hence consume a smaller area than when the circuit is driven by the external power supply voltage EXVDD (for example of 1.8V) as conventional.

    摘要翻译： 在本半导体器件中，正的驱动泵电路由外部电源电位EXVDD（例如1.8V）驱动以产生正电压VPC（例如2.4V）。 用于内部操作的负泵电路由正电压VPC驱动以产生对于字线的擦除或类似的内部操作所需的负电压VNA（例如-9.2V）。 用于内部操作的负泵电路可以具有较少数量的泵级，并且因此消耗比通过外部电源电压EXVDD（例如1.8V）驱动电路时更小的面积。

    Semiconductor memory device capable of accurate and stable operation
    7.
    发明申请
    Semiconductor memory device capable of accurate and stable operation 有权
    半导体存储器件能够准确稳定运行

    公开(公告)号：US20050058012A1

    公开(公告)日：2005-03-17

    申请号：US10938615

    申请日：2004-09-13

    申请人： Tadaaki Yamauchi ,  Kiyohiro Furutani

    发明人： Tadaaki Yamauchi ,  Kiyohiro Furutani

    IPC分类号： G11C16/02 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C11/407 ,  G11C16/06 ,  H04N5/95

    CPC分类号： G11C7/109 ,  G11C7/10 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093

    摘要： An external clock generating circuit generates a mode indicating signal at the “H” level and generates an external clock signal synchronized with a write command buffer signal, when a semiconductor memory device is not in an internal operation mode. When the semiconductor memory device enters an internal operation mode and the mode indicating signal makes a transition from “H” to “L”, the external clock signal is fixed at the “L” level. The external clock signal is not supplied to an external CUI, and the external CUI is set in a state in which reception of any external command is prohibited. Until the end of asynchronous reset, the mode indicating signal is kept at the “L” level, and thereafter raised to the “H” level, so that malfunction caused by an input of an external command during asynchronous reset period can be avoided.

    摘要翻译： 当半导体存储器件不处于内部操作模式时，外部时钟产生电路产生“H”电平的模式指示信号并产生与写入命令缓冲器信号同步的外部时钟信号。 当半导体存储器件进入内部操作模式并且模式指示信号从“H”转变为“L”时，外部时钟信号固定在“L”电平。 外部时钟信号不提供给外部CUI，外部CUI被设置为禁止接收任何外部命令的状态。 直到异步复位结束为止，模式指示信号保持在“L”电平，然后升至“H”电平，从而避免在异步复位期间由外部指令输入引起的故障。

    Semiconductor device with pump circuit
    8.
    发明授权
    Semiconductor device with pump circuit 有权
    带泵电路的半导体器件

    公开(公告)号：US07365578B2

    公开(公告)日：2008-04-29

    申请号：US11822184

    申请日：2007-07-03

    申请人： Minoru Senda ,  Kiyohiro Furutani ,  Taku Ogura ,  Shigehiro Kuge ,  Satoshi Kawasaki ,  Tadaaki Yamauchi

    发明人： Minoru Senda ,  Kiyohiro Furutani ,  Taku Ogura ,  Shigehiro Kuge ,  Satoshi Kawasaki ,  Tadaaki Yamauchi

    IPC分类号： H03K3/00

    CPC分类号： G11C16/30 ,  G11C5/145 ,  G11C16/04 ,  H02M3/073 ,  H02M2003/071 ,  H02M2003/075 ,  H02M2003/077 ,  H03K3/356113

    摘要： In the present semiconductor device a positive, driving pump circuit is driven by an external power supply potential EXVDD (for example of 1.8V) to generate a positive voltage VPC (for example of 2.4V). A negative pump circuit for internal operation is driven by the positive voltage VPC to generate a negative voltage VNA (for example of −9.2V) required in an erasure or similar internal operation for a word line. The negative pump circuit for internal operation can have a smaller number of stages of pump and hence consume a smaller area than when the circuit is driven by the external power supply voltage EXVDD (for example of 1.8V) as conventional.

    摘要翻译： 在本半导体器件中，正的驱动泵电路由外部电源电位EXVDD（例如1.8V）驱动以产生正电压VPC（例如2.4V）。 用于内部操作的负泵电路由正电压VPC驱动以产生对于字线的擦除或类似的内部操作所需的负电压VNA（例如-9.2V）。 用于内部操作的负泵电路可以具有较少数量的泵级，并且因此消耗比通过外部电源电压EXVDD（例如1.8V）驱动电路时更小的面积。

    Semiconductor memory device capable of accurate and stable operation
    10.
    发明授权
    Semiconductor memory device capable of accurate and stable operation 有权
    半导体存储器件能够准确稳定运行

    公开(公告)号：US07042769B2

    公开(公告)日：2006-05-09

    申请号：US10938615

    申请日：2004-09-13

    申请人： Tadaaki Yamauchi ,  Kiyohiro Furutani

    发明人： Tadaaki Yamauchi ,  Kiyohiro Furutani

    IPC分类号： G11C7/00 ,  G11C8/00

    CPC分类号： G11C7/109 ,  G11C7/10 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093

    摘要： An external clock generating circuit generates a mode indicating signal at the “H” level and generates an external clock signal synchronized with a write command buffer signal, when a semiconductor memory device is not in an internal operation mode. When the semiconductor memory device enters an internal operation mode and the mode indicating signal makes a transition from “H” to “L”, the external clock signal is fixed at the “L” level. The external clock signal is not supplied to an external CUI, and the external CUI is set in a state in which reception of any external command is prohibited. Until the end of asynchronous reset, the mode indicating signal is kept at the “L” level, and thereafter raised to the “H” level, so that malfunction caused by an input of an external command during asynchronous reset period can be avoided.

    摘要翻译： 当半导体存储器件不处于内部操作模式时，外部时钟产生电路产生“H”电平的模式指示信号并产生与写入命令缓冲器信号同步的外部时钟信号。 当半导体存储器件进入内部操作模式并且模式指示信号从“H”转变为“L”时，外部时钟信号固定在“L”电平。 外部时钟信号不提供给外部CUI，外部CUI被设置为禁止接收任何外部命令的状态。 直到异步复位结束为止，模式指示信号保持在“L”电平，然后升至“H”电平，从而避免在异步复位期间由外部指令输入引起的故障。