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公开(公告)号：US20130168793A1
公开(公告)日：2013-07-04
申请号：US13819559
申请日：2011-09-01
IPC分类号： H01L31/02
CPC分类号： H01L31/02002 , H01L31/022416 , H01L31/03046 , H01L31/035281 , H01L31/1075 , Y02E10/544
摘要： An APD is provided with the semi-insulating substrate, a first mesa having a first laminate constitution in which a p-type electrode layer, a p-type light absorbing layer, a light absorbing layer with a low impurity concentration, a band gap inclined layer, a p-type electric field control layer, an avalanche multiplier layer, an n-type electric field control layer, and an electron transit layer with a low impurity concentration are stacked in this order on a surface of the semi-insulating substrate, a second mesa having an outer circumference provided inside an outer circumference of the first mesa as viewed from the laminating direction and having a second laminate constitution in which an n-type electrode buffer layer and an n-type electrode layer are stacked in this order on a surface on the electron transit layer side, and a depletion control region that is provided in layers on the second mesa side relative to the p-type electric field control layer, formed in an encircling portion provided inside an outer circumference of the first mesa and encircling an outer circumference of the second mesa, and prevents the encircling portion of the p-type electric field control layer from being depleted when bias is applied.
摘要翻译： APD设置有半绝缘基板，第一台面具有第一层叠结构，其中p型电极层，p型光吸收层，具有低杂质浓度的光吸收层，带隙倾斜 层叠，p型电场控制层，雪崩乘法器层，n型电场控制层和具有低杂质浓度的电子传输层依次层叠在半绝缘基板的表面上， 第二台面，其具有从层叠方向观察时设置在第一台面的外周的外周，并且具有第二层叠结构，其中n型电极缓冲层和n型电极层依次层叠在 电子转移层侧的表面和相对于p型电场控制层设置在第二台面侧的层的耗尽控制区域，形成在环状端口 n设置在第一台面的外周内并且围绕第二台面的外周，并且在施加偏压时防止p型电场控制层的环绕部分耗尽。
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公开(公告)号：US08729602B2
公开(公告)日：2014-05-20
申请号：US13819279
申请日：2011-09-01
IPC分类号： H01L31/107 , H01L21/00
CPC分类号： H01L31/035281 , H01L31/03046 , H01L31/1075 , Y02E10/544
摘要： An APD is provided with a semi-insulating substrate, a first mesa having a first laminate constitution in which a p-type electrode layer, a p-type light absorbing layer, a light absorbing layer with a low impurity concentration, a band gap inclined layer, a p-type electric field control layer, an avalanche multiplier layer, an n-type electric field control layer, and an electron transit layer with a low impurity concentration are stacked in this order on a surface of the semi-insulating substrate, a second mesa having an outer circumference provided inside an outer circumference of the first mesa as viewed from the laminating direction and having a second laminate constitution in which an n-type electrode buffer layer and an n-type electrode layer are stacked in this order on a surface on the electron transit layer side of the first mesa, and in the APD, a total donor concentration of the n-type electric field control layer is lower than a total acceptor concentration of the p-type electric field control layer in a range of 2×1011 to 1×1012/cm2.
摘要翻译： APD设置有半绝缘基板，第一台面具有第一层叠结构，其中p型电极层，p型光吸收层，具有低杂质浓度的光吸收层，带隙倾斜 层叠，p型电场控制层，雪崩乘法器层，n型电场控制层和具有低杂质浓度的电子传输层依次层叠在半绝缘基板的表面上， 第二台面，其具有从层叠方向观察时设置在第一台面的外周的外周，并且具有第二层叠结构，其中n型电极缓冲层和n型电极层依次层叠在 在第一台面的电子转移层侧的表面，在APD中，n型电场控制层的供体总供体浓度低于p型电解质的总受体浓度 在2×1011到1×1012 / cm2的范围内的场域控制层。
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公开(公告)号：US09006854B2
公开(公告)日：2015-04-14
申请号：US13819559
申请日：2011-09-01
IPC分类号： H01L31/107 , H01L31/02 , H01L31/0224
CPC分类号： H01L31/02002 , H01L31/022416 , H01L31/03046 , H01L31/035281 , H01L31/1075 , Y02E10/544
摘要： An APD is provided with the semi-insulating substrate, a first mesa having a first laminate constitution in which a p-type electrode layer, a p-type light absorbing layer, a light absorbing layer with a low impurity concentration, a band gap inclined layer, a p-type electric field control layer, an avalanche multiplier layer, an n-type electric field control layer, and an electron transit layer with a low impurity concentration are stacked in this order on a surface of the semi-insulating substrate, a second mesa having an outer circumference provided inside an outer circumference of the first mesa as viewed from the laminating direction and having a second laminate constitution in which an n-type electrode buffer layer and an n-type electrode layer are stacked in this order on a surface on the electron transit layer side, and a depletion control region that is provided in layers on the second mesa side relative to the p-type electric field control layer, formed in an encircling portion provided inside an outer circumference of the first mesa and encircling an outer circumference of the second mesa, and prevents the encircling portion of the p-type electric field control layer from being depleted when bias is applied.
摘要翻译： APD设置有半绝缘基板，第一台面具有第一层叠结构，其中p型电极层，p型光吸收层，具有低杂质浓度的光吸收层，带隙倾斜 层叠，p型电场控制层，雪崩乘法器层，n型电场控制层和具有低杂质浓度的电子传输层依次层叠在半绝缘基板的表面上， 第二台面，其具有从层叠方向观察时设置在第一台面的外周的外周，并且具有第二层叠结构，其中n型电极缓冲层和n型电极层依次层叠在 电子转移层侧的表面和相对于p型电场控制层设置在第二台面侧的层的耗尽控制区域，形成在环状端口 n设置在第一台面的外周内并且围绕第二台面的外周，并且在施加偏压时防止p型电场控制层的环绕部分耗尽。
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公开(公告)号：US20130154045A1
公开(公告)日：2013-06-20
申请号：US13819279
申请日：2011-09-01
IPC分类号： H01L31/0352
CPC分类号： H01L31/035281 , H01L31/03046 , H01L31/1075 , Y02E10/544
摘要： An APD is provided with a semi-insulating substrate, a first mesa having a first laminate constitution in which a p-type electrode layer, a p-type light absorbing layer, a light absorbing layer with a low impurity concentration, a band gap inclined layer, a p-type electric field control layer, an avalanche multiplier layer, an n-type electric field control layer, and an electron transit layer with a low impurity concentration are stacked in this order on a surface of the semi-insulating substrate, a second mesa having an outer circumference provided inside an outer circumference of the first mesa as viewed from the laminating direction and having a second laminate constitution in which an n-type electrode buffer layer and an n-type electrode layer are stacked in this order on a surface on the electron transit layer side of the first mesa, and in the APD, a total donor concentration of the n-type electric field control layer is lower than a total acceptor concentration of the p-type electric field control layer in a range of 2×1011 to 1×1012/cm2.
摘要翻译： APD设置有半绝缘基板，第一台面具有第一层叠结构，其中p型电极层，p型光吸收层，具有低杂质浓度的光吸收层，带隙倾斜 层叠，p型电场控制层，雪崩乘法器层，n型电场控制层和具有低杂质浓度的电子传输层依次层叠在半绝缘基板的表面上， 第二台面，其具有从层叠方向观察时设置在第一台面的外周的外周，并且具有第二层叠结构，其中n型电极缓冲层和n型电极层依次层叠在 在第一台面的电子转移层侧的表面，并且在APD中，n型电场控制层的总施主浓度低于p型电子的总受主浓度 在2×1011到1×1012 / cm2的范围内的场域控制层。
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公开(公告)号：US20110241150A1
公开(公告)日：2011-10-06
申请号：US13133990
申请日：2009-12-11
IPC分类号： H01L31/0224
CPC分类号： H01L31/1075
摘要： An electron injected APD with an embedded n electrode structure in which edge breakdown can be suppressed without controlling the doping profile of an n-type region of the embedded n electrode structure with high precision. The APD comprising a buffer layer with a low ionization rate is inserted between an n electrode connecting layer and an avalanche multiplication layer. Specifically, the APD is an electron injected APD in which an n electrode layer, the n electrode connecting layer, the buffer layer, the avalanche multiplication layer, an electric field control layer, a band gap gradient layer, a low-concentration light absorbing layer, a p-type light absorbing layer, and a p electrode layer are sequentially stacked, and a light absorbing portion that includes at least the low-concentration light absorbing layer and the p-type light absorbing layer forms a mesa shape.
摘要翻译： 具有嵌入式n电极结构的电子注入APD，其中可以抑制边缘击穿而不以高精度控制嵌入式n电极结构的n型区域的掺杂分布。 包括具有低电离速率的缓冲层的APD插入在n电极连接层和雪崩倍增层之间。 具体地，APD是电子注入APD，其中n电极层，n电极连接层，缓冲层，雪崩倍增层，电场控制层，带隙梯度层，低浓度光吸收层 p型光吸收层和ap电极层依次层叠，并且至少包含低浓度光吸收层和p型光吸收层的光吸收部形成台面形状。
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公开(公告)号：US08754445B2
公开(公告)日：2014-06-17
申请号：US13981050
申请日：2012-01-20
IPC分类号： H01L31/107
CPC分类号： H01L29/0615 , G02F1/025 , G02F2001/0157 , H01L29/0692 , H01L29/0821 , H01L29/205 , H01L29/41708 , H01L29/42304 , H01L29/7371 , H01L31/03046 , H01L31/035281 , H01L31/105 , Y02E10/544
摘要： A layer in which the potential level difference normally unrequired for device operation is generated is positively inserted in a device structure. The potential level difference has such a function that even if a semiconductor having a small bandgap is exposed on a mesa side surface, a potential drop amount of the portion is suppressed, and a leakage current inconvenient for device operation can be reduced. This effect can be commonly obtained for a heterostructure bipolar transistor, a photodiode, an electroabsorption modulator, and so on. In the photodiode, since the leakage current is alleviated, the device size can be reduced, so that in addition to improvement of operating speed with a reduction in series resistance, it is advantageous that the device can be densely disposed in an array.
摘要翻译： 产生通常不需要用于器件操作的电位电平差的层被积极地插入到器件结构中。 电位差具有这样的功能：即使具有小的带隙的半导体暴露在台面侧表面上，也能够抑制该部分的电位下降量，并且能够减少不利于器件操作的漏电流。 对于异质结双极晶体管，光电二极管，电吸收调制器等，通常可以获得这种效果。 在光电二极管中，由于泄漏电流被减轻，所以能够减小器件尺寸，除了随着串联电阻的降低而提高工作速度之外，还可以将器件密集地排列成阵列。
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公开(公告)号：US08575650B2
公开(公告)日：2013-11-05
申请号：US13133990
申请日：2009-12-11
IPC分类号： H01L31/107
CPC分类号： H01L31/1075
摘要： An electron injected APD with an embedded n electrode structure in which edge breakdown can be suppressed without controlling the doping profile of an n-type region of the embedded n electrode structure with high precision. The APD comprising a buffer layer with a low ionization rate is inserted between an n electrode connecting layer and an avalanche multiplication layer. Specifically, the APD is an electron injected APD in which an n electrode layer, the n electrode connecting layer, the buffer layer, the avalanche multiplication layer, an electric field control layer, a band gap gradient layer, a low-concentration light absorbing layer, a p-type light absorbing layer, and a p electrode layer are sequentially stacked, and a light absorbing portion that includes at least the low-concentration light absorbing layer and the p-type light absorbing layer forms a mesa shape.
摘要翻译： 具有嵌入式n电极结构的电子注入APD，其中可以抑制边缘击穿而不以高精度控制嵌入式n电极结构的n型区域的掺杂分布。 包括具有低电离速率的缓冲层的APD插入在n电极连接层和雪崩倍增层之间。 具体地，APD是电子注入APD，其中n电极层，n电极连接层，缓冲层，雪崩倍增层，电场控制层，带隙梯度层，低浓度光吸收层 p型光吸收层和ap电极层依次层叠，并且至少包含低浓度光吸收层和p型光吸收层的光吸收部形成台面形状。
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公开(公告)号：US20130313608A1
公开(公告)日：2013-11-28
申请号：US13981050
申请日：2012-01-20
IPC分类号： H01L29/06
CPC分类号： H01L29/0615 , G02F1/025 , G02F2001/0157 , H01L29/0692 , H01L29/0821 , H01L29/205 , H01L29/41708 , H01L29/42304 , H01L29/7371 , H01L31/03046 , H01L31/035281 , H01L31/105 , Y02E10/544
摘要： A layer in which the potential level difference normally unrequired for device operation is generated is positively inserted in a device structure. The potential level difference has such a function that even if a semiconductor having a small bandgap is exposed on a mesa side surface, a potential drop amount of the portion is suppressed, and a leakage current inconvenient for device operation can be reduced. This effect can be commonly obtained for a heterostructure bipolar transistor, a photodiode, an electroabsorption modulator, and so on. In the photodiode, since the leakage current is alleviated, the device size can be reduced, so that in addition to improvement of operating speed with a reduction in series resistance, it is advantageous that the device can be densely disposed in an array.
摘要翻译： 产生通常不需要用于器件操作的电位电平差的层被积极地插入到器件结构中。 电位差具有这样的功能：即使具有小的带隙的半导体暴露在台面侧表面上，也能够抑制该部分的电位下降量，并且能够减少不利于器件操作的漏电流。 对于异质结双极晶体管，光电二极管，电吸收调制器等，通常可以获得这种效果。 在光电二极管中，由于泄漏电流被减轻，所以能够减小器件尺寸，除了随着串联电阻的降低而提高工作速度之外，还可以将器件密集地排列成阵列。
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公开(公告)号：US07242038B2
公开(公告)日：2007-07-10
申请号：US10560756
申请日：2005-06-24
IPC分类号： H01L29/739
CPC分类号： H01L29/0817 , H01L29/205 , H01L29/7371
摘要： An n-type InP sub collector layer 2 heavily doped with silicon (Si), an InP collector layer 3, a p-type GaAs(0.51)Sb(0.49) base layer 4 heavily doped with carbon (C), an n-type In(1-y)Al(y)P emitter layer 7 doped with Si, an n-type InP cap layer 8 heavily doped with Si, and an n-type In(0.53)Ga(0.47)As contact layer 9 heavily doped with Si are stacked on a substrate 1.
摘要翻译： 重掺杂有硅（Si），InP集电极层3，p型GaAs（0.51）Sb（0.49））碱的n型InP子集电极层2 重掺杂碳（C）的层4，掺杂Si的n型In（1-y）Al（y）P发射极层7，n型 重掺杂Si的InP覆盖层8以及重掺杂Si的接触层9堆叠在衬底1上的n型In（0.53）Ga（0.47） 。
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公开(公告)号：US20060231859A1
公开(公告)日：2006-10-19
申请号：US10560756
申请日：2005-06-24
IPC分类号： H01L29/732
CPC分类号： H01L29/0817 , H01L29/205 , H01L29/7371
摘要： An n-type InP sub collector layer 2 heavily doped with silicon (Si), an InP collector layer 3, a p-type GaAs(0.51)Sb(0.49) base layer 4 heavily doped with carbon (C), an n-type In(1-y)Al(y)P emitter layer 7 doped with Si, an n-type InP cap layer 8 heavily doped with Si, and an n-type In(0.53)Ga(0.47)As contact layer 9 heavily doped with Si are stacked on a substrate 1.
摘要翻译： 重掺杂有硅（Si），InP集电极层3，p型GaAs（0.51）Sb（0.49））碱的n型InP子集电极层2 重掺杂碳（C）的层4，掺杂Si的n型In（1-y）Al（y）P发射极层7，n型 重掺杂Si的InP覆盖层8以及重掺杂Si的接触层9堆叠在衬底1上的n型In（0.53）Ga（0.47） 。
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