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    Phase interpolator and delay locked-loop circuit
    1.
    发明授权
    Phase interpolator and delay locked-loop circuit 有权
    相位内插器和延迟锁相环电路

    公开(公告)号：US08373475B2

    公开(公告)日：2013-02-12

    申请号：US13270509

    申请日：2011-10-11

    申请人： Tae-Sik Na ,  Yang-Ki Kim

    发明人： Tae-Sik Na ,  Yang-Ki Kim

    IPC分类号： H03L7/06

    CPC分类号： H03H11/16 ,  H03L7/0818

    摘要： A phase interpolator includes a delay difference detector and a phase interpolation driver. The delay difference detector receives a delay code to detect a delay difference. The phase interpolation driver includes two or more driver blocks complementarily operating, and the phase interpolation driver interpolate two input signals in response to the delay difference to provide an interpolated output signal. Each of two or more driver blocks includes a plurality of unit drivers, each input of the unit drivers is commonly connected, and each delay of the two or more driver blocks is varied according to the delay difference.

    摘要翻译： 相位插值器包括延迟差检测器和相位插值驱动器。 延迟差检测器接收延迟码以检测延迟差。 相位插值驱动器包括两个或更多个驱动器块互补操作，并且相位插值驱动器响应于延迟差内插两个输入信号以提供内插输出信号。 两个或更多个驱动器块中的每一个包括多个单元驱动器，单元驱动器的每个输入共同连接，并且两个或更多个驱动器块的每个延迟根据延迟差异而变化。

    PHASE INTERPOLATOR AND DELAY LOCKED-LOOP CIRCUIT
    2.
    发明申请
    PHASE INTERPOLATOR AND DELAY LOCKED-LOOP CIRCUIT 有权
    相位插补器和延迟锁定环路

    公开(公告)号：US20120086486A1

    公开(公告)日：2012-04-12

    申请号：US13270509

    申请日：2011-10-11

    申请人： Tae-Sik NA ,  Yang-Ki Kim

    发明人： Tae-Sik NA ,  Yang-Ki Kim

    IPC分类号： H03L7/08 ,  H03H11/16

    CPC分类号： H03H11/16 ,  H03L7/0818

    摘要： A phase interpolator includes a delay difference detector and a phase interpolation driver. The delay difference detector receives a delay code to detect a delay difference. The phase interpolation driver includes two or more driver blocks complementarily operating, and the phase interpolation driver interpolate two input signals in response to the delay difference to provide an interpolated output signal. Each of two or more driver blocks includes a plurality of unit drivers, each input of the unit drivers is commonly connected, and each delay of the two or more driver blocks is varied according to the delay difference.

    摘要翻译： 相位插值器包括延迟差检测器和相位插值驱动器。 延迟差检测器接收延迟码以检测延迟差。 相位插值驱动器包括两个或更多个驱动器块互补操作，并且相位插值驱动器响应于延迟差内插两个输入信号以提供内插输出信号。 两个或更多个驱动器块中的每一个包括多个单元驱动器，单元驱动器的每个输入共同连接，并且两个或更多个驱动器块的每个延迟根据延迟差异而变化。

    Semiconductor Devices Including Design for Test Capabilities and Semiconductor Modules and Test Systems Including Such Devices
    3.
    发明申请
    Semiconductor Devices Including Design for Test Capabilities and Semiconductor Modules and Test Systems Including Such Devices 有权
    包括用于测试能力的设计的半导体器件和包括这些器件的半导体模块和测试系统

    公开(公告)号：US20110115509A1

    公开(公告)日：2011-05-19

    申请号：US12915314

    申请日：2010-10-29

    申请人： Seok-Il Kim ,  Ho-Suk Lee ,  You-Keun Han ,  Yang-Ki Kim

    发明人： Seok-Il Kim ,  Ho-Suk Lee ,  You-Keun Han ,  Yang-Ki Kim

    IPC分类号： G01R31/3187

    CPC分类号： G01R31/31717 ,  G01R31/2884 ,  G01R31/3004 ,  G01R31/3185 ,  H01L22/34

    摘要： A semiconductor device includes a resistor terminal, a reference voltage generator and a detector. The resistor terminal is connected to an external resistor. The reference voltage generator generates at least one reference voltage. The detector generates a detection signal based at least in part on a resistor terminal voltage and the at least one reference voltage. The detection signal indicates a state of an electrical connection to the resistor terminal. The resistor terminal voltage is a voltage at the resistor terminal.

    摘要翻译： 半导体器件包括电阻器端子，参考电压发生器和检测器。 电阻端子连接到外部电阻。 参考电压发生器产生至少一个参考电压。 检测器至少部分地基于电阻器端子电压和至少一个参考电压产生检测信号。 检测信号表示与电阻端子的电连接的状态。 电阻端子电压是电阻端子处的电压。

    Data receiver, semiconductor device and memory device including the same
    4.
    发明授权
    Data receiver, semiconductor device and memory device including the same 有权
    数据接收器，半导体器件和包括其的存储器件

    公开(公告)号：US08559241B2

    公开(公告)日：2013-10-15

    申请号：US13110161

    申请日：2011-05-18

    申请人： Sung-Joo Park ,  Jea-Eun Lee ,  Jung-Joon Lee ,  Yang-Ki Kim ,  Kyoung-Sun Kim

    发明人： Sung-Joo Park ,  Jea-Eun Lee ,  Jung-Joon Lee ,  Yang-Ki Kim ,  Kyoung-Sun Kim

    IPC分类号： G11C7/10

    CPC分类号： G11C7/1078 ,  G11C7/1084 ,  G11C8/06

    摘要： A data receiver includes a first buffer circuit and a second buffer circuit. The first buffer circuit varies a resistance of a data path and a resistance of a reference voltage path based on a plurality of control signals, and adjusts a voltage level of an input data signal and a level of a reference voltage to generate an internal data signal and an internal reference voltage based on the varied resistance of the data path and the varied resistance of the reference voltage path. The second buffer circuit compares the internal data signal with the internal reference voltage to generate a data signal.

    摘要翻译： 数据接收机包括第一缓冲电路和第二缓冲电路。 第一缓冲电路基于多个控制信号改变数据路径的电阻和参考电压路径的电阻，并且调整输入数据信号的电压电平和参考电压的电平以产生内部数据信号 以及基于数据路径的变化的电阻和参考电压路径的变化的电阻的内部参考电压。 第二缓冲电路将内部数据信号与内部参考电压进行比较以产生数据信号。

    DATA RECEIVER, SEMICONDUCTOR DEVICE AND MEMORY DEVICE INCLUDING THE SAME
    6.
    发明申请
    DATA RECEIVER, SEMICONDUCTOR DEVICE AND MEMORY DEVICE INCLUDING THE SAME 有权
    数据接收器，半导体器件和包括其的存储器件

    公开(公告)号：US20120014156A1

    公开(公告)日：2012-01-19

    申请号：US13110161

    申请日：2011-05-18

    申请人： Sung-Joo PARK ,  Jea-Eun Lee ,  Jung-Joon Lee ,  Yang-Ki Kim ,  Kyoung-Sun Kim

    发明人： Sung-Joo PARK ,  Jea-Eun Lee ,  Jung-Joon Lee ,  Yang-Ki Kim ,  Kyoung-Sun Kim

    IPC分类号： G11C5/02 ,  G11C7/10 ,  H03L5/00

    CPC分类号： G11C7/1078 ,  G11C7/1084 ,  G11C8/06

    摘要： A data receiver includes a first buffer circuit and a second buffer circuit. The first buffer circuit varies a resistance of a data path and a resistance of a reference voltage path based on a plurality of control signals, and adjusts a voltage level of an input data signal and a level of a reference voltage to generate an internal data signal and an internal reference voltage based on the varied resistance of the data path and the varied resistance of the reference voltage path. The second buffer circuit compares the internal data signal with the internal reference voltage to generate a data signal.

    摘要翻译： 数据接收机包括第一缓冲电路和第二缓冲电路。 第一缓冲电路基于多个控制信号改变数据路径的电阻和参考电压路径的电阻，并且调整输入数据信号的电压电平和参考电压的电平以产生内部数据信号 以及基于数据路径的变化的电阻和参考电压路径的变化的电阻的内部参考电压。 第二缓冲电路将内部数据信号与内部参考电压进行比较以产生数据信号。

    Memory devices and systems including write leveling operations and methods of performing write leveling operations in memory devices and systems
    7.
    发明申请
    Memory devices and systems including write leveling operations and methods of performing write leveling operations in memory devices and systems 有权
    包括写入调平操作的存储器件和系统以及在存储器件和系统中执行写调平操作的方法

    公开(公告)号：US20110047319A1

    公开(公告)日：2011-02-24

    申请号：US12584937

    申请日：2009-09-15

    申请人： Young-Jin Jeon ,  Yang-Ki Kim

    发明人： Young-Jin Jeon ,  Yang-Ki Kim

    IPC分类号： G06F12/00 ,  G11C7/00 ,  G06F12/02

    CPC分类号： G06F13/4243 ,  Y02D10/14 ,  Y02D10/151

    摘要： A memory device controller having a write leveling mode of operation comprises: a clock generator that generates a periodic clock signal for transmission to a memory device; a data strobe generator that generates a data strobe signal for transmission to the memory device; and a control unit that generates command signals for transmission to the memory device, the controller, during operation in the write leveling mode, generating a command signal and a write leveling control signal for transmission to the memory device.

    摘要翻译： 一种具有写入均衡操作模式的存储器件控制器，包括：时钟发生器，其产生用于传输到存储器件的周期性时钟信号; 数据选通发生器，其产生用于传输到存储器件的数据选通信号; 以及控制单元，其在写入调平模式下的操作期间产生用于传输到存储器件，控制器的命令信号，产生用于传输到存储器件的命令信号和写入调平控制信号。

    Memory devices and systems including write leveling operations and methods of performing write leveling operations in memory devices and systems
    8.
    发明授权
    Memory devices and systems including write leveling operations and methods of performing write leveling operations in memory devices and systems 有权
    包括写入调平操作的存储器件和系统以及在存储器件和系统中执行写调平操作的方法

    公开(公告)号：US08386737B2

    公开(公告)日：2013-02-26

    申请号：US12584937

    申请日：2009-09-15

    申请人： Young-Jin Jeon ,  Yang-Ki Kim

    发明人： Young-Jin Jeon ,  Yang-Ki Kim

    IPC分类号： G06F12/00 ,  G11C7/00 ,  G11C7/10

    CPC分类号： G06F13/4243 ,  Y02D10/14 ,  Y02D10/151

    摘要： A memory device controller having a write leveling mode of operation comprises: a clock generator that generates a periodic clock signal for transmission to a memory device; a data strobe generator that generates a data strobe signal for transmission to the memory device; and a control unit that generates command signals for transmission to the memory device, the controller, during operation in the write leveling mode, generating a command signal and a write leveling control signal for transmission to the memory device.

    摘要翻译： 一种具有写入均衡操作模式的存储器件控制器包括：时钟发生器，其产生用于传输到存储器件的周期性时钟信号; 数据选通发生器，其产生用于传输到存储器件的数据选通信号; 以及控制单元，其在写入调平模式下的操作期间产生用于传输到存储器件，控制器的命令信号，产生用于传输到存储器件的命令信号和写入调平控制信号。