公开(公告)号：US20110069555A1

公开(公告)日：2011-03-24

申请号：US12955984

申请日：2010-11-30

申请人： Tae-Whan Kim ,  Kae-Dal Kwack ,  Sang-Su Park

发明人： Tae-Whan Kim ,  Kae-Dal Kwack ,  Sang-Su Park

IPC分类号： G11C16/26 ,  G11C16/10

CPC分类号： H01L29/7887 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7923

摘要： A non-volatile memory device includes a semiconductor substrate, first and second control gates, and first and second charge storage patterns. The semiconductor substrate includes a protruding active pin having a source region, a drain region and a channel region located between the source and drain regions. The first control gate is located on a first sidewall of the channel region, and the second control gate is located on a second sidewall of the channel region. The second control gate is separated from the first control gate. The first charge storage pattern is located between the first sidewall and the first control gate, and the second charge storage pattern is located between the second sidewall and the second control gate.

摘要翻译： 非易失性存储器件包括半导体衬底，第一和第二控制栅极以及第一和第二电荷存储模式。 半导体衬底包括具有源极区，漏极区和位于源极和漏极区之间的沟道区的突出的有源管脚。 第一控制栅极位于沟道区的第一侧壁上，第二控制栅位于沟道区的第二侧壁上。 第二控制栅极与第一控制栅极分离。 第一电荷存储图案位于第一侧壁和第一控制栅极之间，第二电荷存储图案位于第二侧壁和第二控制栅极之间。

公开(公告)号：US07927951B2

公开(公告)日：2011-04-19

申请号：US12955984

申请日：2010-11-30

申请人： Tae-Whan Kim ,  Kae-Dal Kwack ,  Sang-Su Park

发明人： Tae-Whan Kim ,  Kae-Dal Kwack ,  Sang-Su Park

IPC分类号： H01L21/336 ,  H01L29/788

CPC分类号： H01L29/7887 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7923

摘要： A non-volatile memory device includes a semiconductor substrate, first and second control gates, and first and second charge storage patterns. The semiconductor substrate includes a protruding active pin having a source region, a drain region and a channel region located between the source and drain regions. The first control gate is located on a first sidewall of the channel region, and the second control gate is located on a second sidewall of the channel region. The second control gate is separated from the first control gate. The first charge storage pattern is located between the first sidewall and the first control gate, and the second charge storage pattern is located between the second sidewall and the second control gate.

摘要翻译： 非易失性存储器件包括半导体衬底，第一和第二控制栅极以及第一和第二电荷存储模式。 半导体衬底包括具有源极区，漏极区和位于源极和漏极区之间的沟道区的突出的有源管脚。 第一控制栅极位于沟道区的第一侧壁上，第二控制栅位于沟道区的第二侧壁上。 第二控制栅极与第一控制栅极分离。 第一电荷存储图案位于第一侧壁和第一控制栅极之间，第二电荷存储图案位于第二侧壁和第二控制栅极之间。

公开(公告)号：US07863673B2

公开(公告)日：2011-01-04

申请号：US12370792

申请日：2009-02-13

申请人： Tae-Whan Kim ,  Kae-Dal Kwack ,  Sang-Su Park

发明人： Tae-Whan Kim ,  Kae-Dal Kwack ,  Sang-Su Park

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L29/7887 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7923

摘要： A non-volatile memory device includes a semiconductor substrate, first and second control gates, and first and second charge storage patterns. The semiconductor substrate includes a protruding active pin having a source region, a drain region and a channel region located between the source and drain regions. The first control gate is located on a first sidewall of the channel region, and the second control gate is located on a second sidewall of the channel region. The second second control gate is separated from the first control gate. The first charge storage pattern is located between the first sidewall and the first control gate, and the second charge storage pattern is located between the second sidewall and the second control gate.

摘要翻译： 非易失性存储器件包括半导体衬底，第一和第二控制栅极以及第一和第二电荷存储模式。 半导体衬底包括具有源极区，漏极区和位于源极和漏极区之间的沟道区的突出的有源管脚。 第一控制栅极位于沟道区的第一侧壁上，第二控制栅位于沟道区的第二侧壁上。 第二第二控制栅极与第一控制栅极分离。 第一电荷存储图案位于第一侧壁和第一控制栅极之间，第二电荷存储图案位于第二侧壁和第二控制栅极之间。

公开(公告)号：US20120124116A1

公开(公告)日：2012-05-17

申请号：US13101356

申请日：2011-05-05

申请人： Hyeong-Seok YU ,  Suk-Jin Kim ,  Sang-Su Park ,  Yong-Surk Lee

发明人： Hyeong-Seok YU ,  Suk-Jin Kim ,  Sang-Su Park ,  Yong-Surk Lee

IPC分类号： G06F7/483

CPC分类号： G06F7/483 ,  H03M7/24

摘要： An apparatus and method for converting data between a floating-point number and an integer is provided. The apparatus includes a data converter configured to determine a sign of input binary data and an output format to which to convert the input binary data and convert the input binary data into a one's complement number based on the sign and the output format of the input binary data, a bias value generator configured to determine whether the input binary data has been rounded up based on a rounding mode of the input binary data and generate a bias value accordingly; and an adder configured to convert the input binary data into a two's complement number by adding the one's complement number and the bias value.

摘要翻译： 提供了一种用于在浮点数和整数之间转换数据的装置和方法。 该装置包括：数据转换器，被配置为基于输入二进制数据的符号和输出格式确定输入二进制数据的符号和输出格式，转换输入的二进制数据并将输入的二进制数据转换为补码 数据，偏置值发生器，被配置为基于所输入的二进制数据的舍入模式来确定输入的二进制数据是否被舍入，并相应地生成偏差值; 以及加法器，被配置为通过将所述补码和偏置值相加来将输入的二进制数据转换成二进制补码。

公开(公告)号：US08119536B2

公开(公告)日：2012-02-21

申请号：US12622738

申请日：2009-11-20

申请人： Sang-Su Park ,  JaeHee Oh

发明人： Sang-Su Park ,  JaeHee Oh

IPC分类号： H01L21/302

CPC分类号： H01L27/2463 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/141

摘要： Provided are a semiconductor device and a method of forming the semiconductor device. The method may include forming a semiconductor pattern on a substrate, forming an interlayer insulating layer including an opening exposing the semiconductor pattern, forming a semiconductor ohmic pattern on the semiconductor pattern, forming an electrode ohmic layer on the semiconductor ohmic pattern, performing a wet etching on the electrode ohmic layer, and forming an electrode pattern on the etched electrode ohmic layer.

摘要翻译： 提供半导体器件和形成半导体器件的方法。 该方法可以包括在衬底上形成半导体图案，形成层间绝缘层，该层间绝缘层包括露出半导体图案的开口，在半导体图案上形成半导体欧姆图案，在半导体图形上形成电极欧姆层，进行湿蚀刻 在电极欧姆层上，并在蚀刻的电极欧姆层上形成电极图案。

公开(公告)号：US08874630B2

公开(公告)日：2014-10-28

申请号：US13101356

申请日：2011-05-05

申请人： Hyeong-Seok Yu ,  Suk-Jin Kim ,  Sang-Su Park ,  Yong-Surk Lee

发明人： Hyeong-Seok Yu ,  Suk-Jin Kim ,  Sang-Su Park ,  Yong-Surk Lee

IPC分类号： G06F7/00 ,  G06F7/483 ,  H03M7/24

CPC分类号： G06F7/483 ,  H03M7/24

摘要： An apparatus and method for converting data between a floating-point number and an integer is provided. The apparatus includes a data converter configured to determine a sign of input binary data and an output format to which to convert the input binary data and convert the input binary data into a one's complement number based on the sign and the output format of the input binary data, a bias value generator configured to determine whether the input binary data has been rounded up based on a rounding mode of the input binary data and generate a bias value accordingly; and an adder configured to convert the input binary data into a two's complement number by adding the one's complement number and the bias value.

摘要翻译： 提供了一种用于在浮点数和整数之间转换数据的装置和方法。 该装置包括：数据转换器，被配置为基于输入二进制数据的符号和输出格式确定输入二进制数据的符号和输出格式，转换输入的二进制数据并将输入的二进制数据转换为补码 数据，偏置值发生器，被配置为基于输入二进制数据的舍入模式来确定输入的二进制数据是否已被舍入，并相应地生成偏差值; 以及加法器，被配置为通过将所述补码和偏置值相加来将输入的二进制数据转换成二进制补码。

公开(公告)号：US20100144141A1

公开(公告)日：2010-06-10

申请号：US12622738

申请日：2009-11-20

申请人： Sang-Su Park ,  JaeHee Oh

发明人： Sang-Su Park ,  JaeHee Oh

IPC分类号： H01L21/3205 ,  H01L47/00

CPC分类号： H01L27/2463 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/141

摘要： Provided are a semiconductor device and a method of forming the semiconductor device. The method may include forming a semiconductor pattern on a substrate, forming an interlayer insulating layer including an opening exposing the semiconductor pattern, forming a semiconductor ohmic pattern on the semiconductor pattern, forming an electrode ohmic layer on the semiconductor ohmic pattern, performing a wet etching on the electrode ohmic layer, and forming an electrode pattern on the etched electrode ohmic layer.

摘要翻译： 提供半导体器件和形成半导体器件的方法。 该方法可以包括在衬底上形成半导体图案，形成层间绝缘层，该层间绝缘层包括露出半导体图案的开口，在半导体图案上形成半导体欧姆图案，在半导体图形上形成电极欧姆层，进行湿蚀刻 在电极欧姆层上，并在蚀刻的电极欧姆层上形成电极图案。