公开(公告)号：US10978412B2

公开(公告)日：2021-04-13

申请号：US16526974

申请日：2019-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Jui Kuo ,  Hui-Jung Tsai ,  Tsao-Lun Chang ,  Tai-Min Chang

IPC: H01L23/66 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01Q1/38 ,  H01Q21/00 ,  C23F1/16 ,  H01L23/31

Abstract: A method including the following steps is provided. A seed layer is formed. Conductive patterns are formed on the seed layer. An etching process with an etchant is performed to remove a portion of the seed layer exposed by the conductive patterns, wherein the etchant includes: 0.1 wt % to 10 wt % of phosphoric acid (H3PO4), 0.1 wt % to 10 wt % of hydrogen peroxide (H2O2), 1 ppm to 20000 ppm of a protective agent, 1 ppm to 20000 ppm of a wetting agent, and a balance amount of a solvent.

公开(公告)号：US20210035928A1

公开(公告)日：2021-02-04

申请号：US16526974

申请日：2019-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Jui Kuo ,  Hui-Jung Tsai ,  Tsao-Lun Chang ,  Tai-Min Chang

IPC: H01L23/66 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01Q1/38 ,  H01Q21/00 ,  C23F1/16

Abstract: A method including the following steps is provided. A seed layer is formed. Conductive patterns are formed on the seed layer. An etching process with an etchant is performed to remove a portion of the seed layer exposed by the conductive patterns, wherein the etchant includes: 0.1 wt % to 10 wt % of phosphoric acid (H3PO4), 0.1 wt % to 10 wt % of hydrogen peroxide (H2O2), 1 ppm to 20000 ppm of a protective agent, 1 ppm to 20000 ppm of a wetting agent, and a balance amount of a solvent.

公开(公告)号：US11508633B2

公开(公告)日：2022-11-22

申请号：US16886755

申请日：2020-05-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Jui Kuo ,  Hui-Jung Tsai ,  Tai-Min Chang ,  Chia-Wei Wang

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/538 ,  H01L25/065 ,  H01L23/00

Abstract: A conductive structure, includes: a plurality of conductive layers; a plurality of conductive pillars being formed on the plurality of conductive layers, respectively; and a molding compound laterally coating the plurality of conductive pillars. Each of the plurality of conductive pillars is a taper-shaped conductive pillar, and is tapered from the conductive layers.

公开(公告)号：US20220336307A1

公开(公告)日：2022-10-20

申请号：US17809924

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Co,.Ltd.

Inventor： Hung-Jui Kuo ,  Tai-Min Chang ,  Hui-Jung Tsai ,  De-Yuan Lu ,  Ming-Tan Lee

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/48

Abstract: A package includes a device die, an encapsulant encapsulating the device die therein, a first plurality of through-vias penetrating through the encapsulant, a second plurality of through-vias penetrating through the encapsulant, and redistribution lines over and electrically coupling to the first plurality of through-vias. The first plurality of through-vias include an array. The second plurality of through-vias are outside of the first array, and the second plurality of through-vias are larger than the first plurality of through-vias.

公开(公告)号：US20230369153A1

公开(公告)日：2023-11-16

申请号：US18361300

申请日：2023-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Jui Kuo ,  Tai-Min Chang ,  Hui-Jung Tsai ,  De-Yuan Lu ,  Ming-Tan Lee

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/48

CPC classification number: H01L23/3121 ,  H01L23/3114 ,  H01L21/561 ,  H01L24/03 ,  H01L23/481 ,  H01L2224/0233

Abstract: A package includes a device die, an encapsulant encapsulating the device die therein, a first plurality of through-vias penetrating through the encapsulant, a second plurality of through-vias penetrating through the encapsulant, and redistribution lines over and electrically coupling to the first plurality of through-vias. The first plurality of through-vias include an array. The second plurality of through-vias are outside of the first array, and the second plurality of through-vias are larger than the first plurality of through-vias.

公开(公告)号：US20210375708A1

公开(公告)日：2021-12-02

申请号：US16886755

申请日：2020-05-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Jui Kuo ,  Hui-Jung Tsai ,  Tai-Min Chang ,  Chia-Wei Wang

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/538 ,  H01L25/065 ,  H01L23/00

Abstract: A conductive structure, includes: a plurality of conductive layers; a plurality of conductive pillars being formed on the plurality of conductive layers, respectively; and a molding compound laterally coating the plurality of conductive pillars. Each of the plurality of conductive pillars is a taper-shaped conductive pillar, and is tapered from the conductive layers.

公开(公告)号：US11823969B2

公开(公告)日：2023-11-21

申请号：US17809924

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Jui Kuo ,  Tai-Min Chang ,  Hui-Jung Tsai ,  De-Yuan Lu ,  Ming-Tan Lee

IPC: H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H01L23/48

CPC classification number: H01L23/3121 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/481 ,  H01L24/03 ,  H01L2224/0233

Abstract: A package includes a device die, an encapsulant encapsulating the device die therein, a first plurality of through-vias penetrating through the encapsulant, a second plurality of through-vias penetrating through the encapsulant, and redistribution lines over and electrically coupling to the first plurality of through-vias. The first plurality of through-vias include an array. The second plurality of through-vias are outside of the first array, and the second plurality of through-vias are larger than the first plurality of through-vias.

公开(公告)号：US11289373B2

公开(公告)日：2022-03-29

申请号：US16504328

申请日：2019-07-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Yuan Teng ,  Bor-Rung Su ,  De-Yuan Lu ,  Hao-Yi Tsai ,  Tin-Hao Kuo ,  Tzung-Hui Lee ,  Tai-Min Chang

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/31 ,  H01L23/00 ,  H01L21/027 ,  H01L21/56

Abstract: A method includes the following steps. A seed layer is formed over a structure having at least one semiconductor die. A first patterned photoresist layer is formed over the seed layer, wherein the first patterned photoresist layer includes a first opening exposing a portion of the seed layer. A metallic wiring is formed in the first opening and on the exposed portion of the seed layer. A second patterned photoresist layer is formed on the first patterned photoresist layer and covers the metallic wiring, wherein the second patterned photoresist layer includes a second opening exposing a portion of the metallic wiring. A conductive via is formed in the second opening and on the exposed portion of the metallic wiring. The first patterned photoresist layer and the second patterned photoresist layer are removed. The metallic wiring and the conductive via are laterally wrapped around with an encapsulant.

公开(公告)号：US20200043782A1

公开(公告)日：2020-02-06

申请号：US16504328

申请日：2019-07-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Yuan Teng ,  Bor-Rung Su ,  De-Yuan Lu ,  Hao-Yi Tsai ,  Tin-Hao Kuo ,  Tzung-Hui Lee ,  Tai-Min Chang

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L21/027

Abstract: A method includes the following steps. A seed layer is formed over a structure having at least one semiconductor die. A first patterned photoresist layer is formed over the seed layer, wherein the first patterned photoresist layer includes a first opening exposing a portion of the seed layer. A metallic wiring is formed in the first opening and on the exposed portion of the seed layer. A second patterned photoresist layer is formed on the first patterned photoresist layer and covers the metallic wiring, wherein the second patterned photoresist layer includes a second opening exposing a portion of the metallic wiring. A conductive via is formed in the second opening and on the exposed portion of the metallic wiring. The first patterned photoresist layer and the second patterned photoresist layer are removed. The metallic wiring and the conductive via are laterally wrapped around with an encapsulant.