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公开(公告)号：US09780209B1
公开(公告)日：2017-10-03
申请号：US15208830
申请日：2016-07-13
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Chih-Fen Chen , Bang-Yu Huang , Chui-Ya Peng
IPC: H01L29/78 , H01L29/08 , H01L29/66 , H01L23/528
CPC classification number: H01L29/7834 , H01L23/5283 , H01L29/665 , H01L29/6659 , H01L29/66636 , H01L29/7843 , H01L29/7848
Abstract: A semiconductor device includes a substrate, a gate stack, at least one epitaxy structure, a dielectric material, and a contact. The gate stack is present on the substrate. The gate spacer is present on a sidewall of the gate stack. The epitaxy structure is partially present in the substrate. The dielectric material is present on the substrate and between the epitaxy structure and the gate spacer. The contact is present on the epitaxy structure, the dielectric material, and the gate spacer.
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公开(公告)号：US20190035697A1
公开(公告)日：2019-01-31
申请号：US15940357
申请日：2018-03-29
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chih-Fen Chen , Tsung-Ying Liu , Yeh-Hsun Fang , Bang-Yu Huang , Chui-Ya Peng
Abstract: In a method for semiconductor processing, a semiconductor substrate is provided. The semiconductor substrate defines at least one first trench therein. The at least one first trench has a first depth (d1). A coating layer is deposited onto the semiconductor substrate using at least one precursor under a setting for a processing temperature (T). The coating layer defines at least one second trench having a second depth (d2) above the at least one first trench. A depth parameter (t) the second depth (d2) relative to the first depth (d1) is determined. The processing temperature (T) is then determined based on a pre-determined standard reference curve comprising a plurality of references depth parameters in a first range as a function of a plurality of reference processing temperatures in a second range.
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公开(公告)号：US20210043524A1
公开(公告)日：2021-02-11
申请号：US17080348
申请日：2020-10-26
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chih-Fen Chen , Tsung-Ying Liu , Yeh-Hsun Fang , Bang-Yu Huang , Chui-Ya Peng
Abstract: In a method for semiconductor processing, a semiconductor substrate is provided. The semiconductor substrate defines at least one first trench therein. The at least one first trench has a first depth (d1). A coating layer is deposited onto the semiconductor substrate using at least one precursor under a setting for a processing temperature (T). The coating layer defines at least one second trench having a second depth (d2) above the at least one first trench. A first depth parameter (t) of the second depth (d2) relative to the first depth (d1) is determined. The processing temperature (T) is then determined based on the first depth parameter (t).
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Patent Agency Ranking
公开(公告)号：US10818563B2
公开(公告)日：2020-10-27
申请号：US16696890
申请日：2019-11-26
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chih-Fen Chen , Tsung-Ying Liu , Yeh-Hsun Fang , Bang-Yu Huang , Chui-Ya Peng
IPC: H01L21/02 , H01L21/66 , C30B29/06 , C30B25/16 , C23C16/02 , H01L21/306 , C23C16/52 , C23C16/24 , C30B25/18
Abstract: In a method for semiconductor processing, a semiconductor substrate is provided. The semiconductor substrate defines at least one first trench therein. The at least one first trench has a first depth (d1). A coating layer is deposited onto the semiconductor substrate using at least one precursor under a setting for a processing temperature (T). The coating layer defines at least one second trench having a second depth (d2) above the at least one first trench. A first depth parameter (t) of the second depth (d2) relative to the first depth (d1) is determined. The processing temperature (T) is then determined based on the first depth parameter (t).
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公开(公告)号：US11610825B2
公开(公告)日：2023-03-21
申请号：US17080348
申请日：2020-10-26
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chih-Fen Chen , Tsung-Ying Liu , Yeh-Hsun Fang , Bang-Yu Huang , Chui-Ya Peng
IPC: H01L21/02 , H01L21/66 , C30B29/06 , C30B25/16 , C23C16/02 , H01L21/306 , C23C16/52 , C23C16/24 , C30B25/18
Abstract: In a method for semiconductor processing, a semiconductor substrate is provided. The semiconductor substrate defines at least one first trench therein. The at least one first trench has a first depth (d1). A coating layer is deposited onto the semiconductor substrate using at least one precursor under a setting for a processing temperature (T). The coating layer defines at least one second trench having a second depth (d2) above the at least one first trench. A first depth parameter (t) of the second depth (d2) relative to the first depth (d1) is determined. The processing temperature (T) is then determined based on the first depth parameter (t).
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公开(公告)号：US20200098650A1
公开(公告)日：2020-03-26
申请号：US16696890
申请日：2019-11-26
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chih-Fen Chen , Tsung-Ying Liu , Yeh-Hsun Fang , Bang-Yu Huang , Chui-Ya Peng
Abstract: In a method for semiconductor processing, a semiconductor substrate is provided. The semiconductor substrate defines at least one first trench therein. The at least one first trench has a first depth (d1). A coating layer is deposited onto the semiconductor substrate using at least one precursor under a setting for a processing temperature (T). The coating layer defines at least one second trench having a second depth (d2) above the at least one first trench. A first depth parameter (t) of the second depth (d2) relative to the first depth (d1) is determined. The processing temperature (T) is then determined based on the first depth parameter (t).
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公开(公告)号：US10515861B2
公开(公告)日：2019-12-24
申请号：US15940357
申请日：2018-03-29
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chih-Fen Chen , Tsung-Ying Liu , Yeh-Hsun Fang , Bang-Yu Huang , Chui-Ya Peng
Abstract: In a method for semiconductor processing, a semiconductor substrate is provided. The semiconductor substrate defines at least one first trench therein. The at least one first trench has a first depth (d1). A coating layer is deposited onto the semiconductor substrate using at least one precursor under a setting for a processing temperature (T). The coating layer defines at least one second trench having a second depth (d2) above the at least one first trench. A depth parameter (t) the second depth (d2) relative to the first depth (d1) is determined. The processing temperature (T) is then determined based on a pre-determined standard reference curve comprising a plurality of references depth parameters in a first range as a function of a plurality of reference processing temperatures in a second range.
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8.发明授权公开(公告)号：US09978634B2
公开(公告)日：2018-05-22
申请号：US14632690
申请日：2015-02-26
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Chun-Hsu Yen , Bang-Yu Huang , Chui-Ya Peng , Ching-Wen Chen
IPC: H01L21/762 , H01L21/02 , H01L29/06 , H01L21/3105 , C23C16/04 , C23C16/505
CPC classification number: H01L21/76224 , C23C16/045 , C23C16/505 , H01L21/02164 , H01L21/02211 , H01L21/02274 , H01L21/31053 , H01L21/31056 , H01L21/76229 , H01L29/0649
Abstract: A method for fabricating a shallow trench isolation includes forming a trench in a substrate, forming a bottom shallow trench isolation dielectric filling a gap of the trench, and forming a top shallow trench isolation dielectric on the bottom shallow trench isolation. The bottom shallow trench isolation dielectric has a concave center portion, and the top shallow trench isolation dielectric is deposited on the bottom shallow trench isolation by a high density plasma chemical vapor deposition process using low deposition to sputter ratio. A semiconductor structure having the shallow trench isolation is also disclosed.
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