公开(公告)号：US20240379364A1

公开(公告)日：2024-11-14

申请号：US18779365

申请日：2024-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Jiun Peng ,  Hsiu-Hao Tsao ,  Shu-Han Chen ,  Chang-Jhih Syu ,  Kuo-Feng Yu ,  Jian-Hao Chen ,  Chih-Hao Yu ,  Chang-Yun Chang

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/285 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

Abstract: In an embodiment, a structure includes: a semiconductor substrate; a gate spacer over the semiconductor substrate, the gate spacer having an upper portion and a lower portion, a first width of the upper portion decreasing continually in a first direction extending away from a top surface of the semiconductor substrate, a second width of the lower portion being constant along the first direction; a gate stack extending along a first sidewall of the gate spacer and the top surface of the semiconductor substrate; and an epitaxial source/drain region adjacent a second sidewall of the gate spacer.

公开(公告)号：US20220351975A1

公开(公告)日：2022-11-03

申请号：US17863006

申请日：2022-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Jiun Peng ,  Hsiu-Hao Tsao ,  Shu-Han Chen ,  Chang-Jhih Syu ,  Kuo-Feng Yu ,  Jian-Hao Chen ,  Chih-Hao Yu ,  Chang-Yun Chang

IPC: H01L21/28 ,  H01L29/78 ,  H01L29/08 ,  H01L29/49 ,  H01L29/45 ,  H01L29/66 ,  H01L21/285 ,  H01L21/3115 ,  H01L21/311 ,  H01L29/423 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/02

Abstract: In an embodiment, a structure includes: a semiconductor substrate; a gate spacer over the semiconductor substrate, the gate spacer having an upper portion and a lower portion, a first width of the upper portion decreasing continually in a first direction extending away from a top surface of the semiconductor substrate, a second width of the lower portion being constant along the first direction; a gate stack extending along a first sidewall of the gate spacer and the top surface of the semiconductor substrate; and an epitaxial source/drain region adjacent a second sidewall of the gate spacer.

公开(公告)号：US20250149388A1

公开(公告)日：2025-05-08

申请号：US19019077

申请日：2025-01-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Jhih Syu ,  Hsiu-Hao Tsao ,  Chih-Hao Yu ,  Yu-Jiun Peng ,  Chang-Yun Chang

IPC: H01L21/66 ,  H10D30/01 ,  H10D64/01 ,  H10D64/27 ,  H10D84/01 ,  H10D84/03

Abstract: A system includes a gate formation tool configured to form a sacrificial gate structure and a replacement gate structure, a device dimension measuring tool configured to measure a dimension of the sacrificial gate structure, and a determination unit configured to pick an etching recipe from a series of etching recipes based on the measured dimension of the sacrificial gate structure. The gate formation tool is also configured to partially remove the sacrificial gate structure using the picked etching recipe to form a gate trench for filling the replacement gate structure therein. A portion of the sacrificial gate structure remains in the gate trench, and the series of etching recipes differ at least in a size of the remaining portion of the sacrificial gate structure.

公开(公告)号：US20210183713A1

公开(公告)日：2021-06-17

申请号：US17075313

申请日：2020-10-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Jhih Syu ,  Chih-Hao Yu ,  Chang-Yun Chang ,  Hsiu-Hao Tsao ,  Yu-Jiun Peng

IPC: H01L21/66 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8234

Abstract: A method of controlling gate formation of a semiconductor device includes acquiring a correlation between gate critical dimensions (CDs) and etching recipes for forming gate trenches; measuring a gate CD on a target wafer; determining an etching recipe based on the correction and the measured gate CD; and performing an etching process on the target wafer to form a gate trench with the determined etching recipe.

公开(公告)号：US20230187288A1

公开(公告)日：2023-06-15

申请号：US18165007

申请日：2023-02-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Jhih Syu ,  Chih-Hao Yu ,  Chang-Yun Chang ,  Hsiu-Hao Tsao ,  Yu-Jiun Peng

IPC: H01L21/66 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L22/20 ,  H01L21/823431 ,  H01L21/823456 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method includes forming an active region on a substrate, forming a sacrificial gate stack engaging the active region, measuring a gate length of the sacrificial gate stack at a height lower than a top surface of the active region, selecting an etching recipe based on the measured gate length of the sacrificial gate stack, etching the sacrificial gate stack with the etching recipe to form a gate trench, and forming a metal gate stack in the gate trench.

公开(公告)号：US20210249271A1

公开(公告)日：2021-08-12

申请号：US16787229

申请日：2020-02-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Jiun Peng ,  Hsiu-Hao Tsao ,  Shu-Han Chen ,  Chang-Jhih Syu ,  Kuo-Feng Yu ,  Jian-Hao Chen ,  Chih-Hao Yu ,  Chang-Yun Chang

IPC: H01L21/28 ,  H01L29/78 ,  H01L29/08 ,  H01L29/49 ,  H01L29/45 ,  H01L21/285 ,  H01L21/3115 ,  H01L21/311 ,  H01L29/66

Abstract: In an embodiment, a structure includes: a semiconductor substrate; a gate spacer over the semiconductor substrate, the gate spacer having an upper portion and a lower portion, a first width of the upper portion decreasing continually in a first direction extending away from a top surface of the semiconductor substrate, a second width of the lower portion being constant along the first direction; a gate stack extending along a first sidewall of the gate spacer and the top surface of the semiconductor substrate; and an epitaxial source/drain region adjacent a second sidewall of the gate spacer.

公开(公告)号：US12198988B2

公开(公告)日：2025-01-14

申请号：US18165007

申请日：2023-02-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Jhih Syu ,  Chih-Hao Yu ,  Chang-Yun Chang ,  Hsiu-Hao Tsao ,  Yu-Jiun Peng

IPC: H01L21/66 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/66

Abstract: A method includes forming an active region on a substrate, forming a sacrificial gate stack engaging the active region, measuring a gate length of the sacrificial gate stack at a height lower than a top surface of the active region, selecting an etching recipe based on the measured gate length of the sacrificial gate stack, etching the sacrificial gate stack with the etching recipe to form a gate trench, and forming a metal gate stack in the gate trench.

公开(公告)号：US11574846B2

公开(公告)日：2023-02-07

申请号：US17075313

申请日：2020-10-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Jhih Syu ,  Chih-Hao Yu ,  Chang-Yun Chang ,  Hsiu-Hao Tsao ,  Yu-Jiun Peng

IPC: H01L21/66 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8234

Abstract: A method of controlling gate formation of a semiconductor device includes acquiring a correlation between gate critical dimensions (CDs) and etching recipes for forming gate trenches; measuring a gate CD on a target wafer; determining an etching recipe based on the correction and the measured gate CD; and performing an etching process on the target wafer to form a gate trench with the determined etching recipe.