公开(公告)号：US11923457B2

公开(公告)日：2024-03-05

申请号：US17850251

申请日：2022-06-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Yu Yang ,  Kai-Chieh Yang ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/08 ,  H01L21/311 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L21/31116 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66795

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a semiconductor fin disposed over a substrate, wherein the semiconductor fin includes a channel region and a source/drain region; a gate structure disposed over the channel region of the semiconductor fin, wherein the gate structure includes a gate spacer and a gate stack; a source/drain structure disposed over the source/drain region of the semiconductor fin; and a fin top hard mask vertically interposed between the gate spacer and the semiconductor fin, wherein the fin top hard mask includes a dielectric layer, and wherein a sidewall of the fin top hard mask directly contacts the gate stack, and another sidewall of the fin top hard mask directly contacts the source/drain structure.

公开(公告)号：US20240105850A1

公开(公告)日：2024-03-28

申请号：US18521794

申请日：2023-11-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Yu Yang ,  Kai-Chieh Yang ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

IPC: H01L29/78 ,  H01L21/311 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/08 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L21/31116 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66795

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a semiconductor fin disposed over a substrate, wherein the semiconductor fin includes a channel region and a source/drain region; a gate structure disposed over the channel region of the semiconductor fin, wherein the gate structure includes a gate spacer and a gate stack; a source/drain structure disposed over the source/drain region of the semiconductor fin; and a fin top hard mask vertically interposed between the gate spacer and the semiconductor fin, wherein the fin top hard mask includes a dielectric layer, and wherein a sidewall of the fin top hard mask directly contacts the gate stack, and another sidewall of the fin top hard mask directly contacts the source/drain structure.

公开(公告)号：US20220328691A1

公开(公告)日：2022-10-13

申请号：US17850251

申请日：2022-06-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Yu Yang ,  Kai-Chieh Yang ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/08 ,  H01L21/311 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/66

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a semiconductor fin disposed over a substrate, wherein the semiconductor fin includes a channel region and a source/drain region; a gate structure disposed over the channel region of the semiconductor fin, wherein the gate structure includes a gate spacer and a gate stack; a source/drain structure disposed over the source/drain region of the semiconductor fin; and a fin top hard mask vertically interposed between the gate spacer and the semiconductor fin, wherein the fin top hard mask includes a dielectric layer, and wherein a sidewall of the fin top hard mask directly contacts the gate stack, and another sidewall of the fin top hard mask directly contacts the source/drain structure.

公开(公告)号：US11374126B2

公开(公告)日：2022-06-28

申请号：US16525832

申请日：2019-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Yu Yang ,  Kai-Chieh Yang ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

IPC: H01L29/78 ,  H01L29/51 ,  H01L21/311 ,  H01L27/088 ,  H01L29/08 ,  H01L21/8234 ,  H01L29/66

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a semiconductor fin disposed over a substrate, wherein the semiconductor fin includes a channel region and a source/drain region; a gate structure disposed over the channel region of the semiconductor fin, wherein the gate structure includes a gate spacer and a gate stack; a source/drain structure disposed over the source/drain region of the semiconductor fin; and a fin top hard mask vertically interposed between the gate spacer and the semiconductor fin, wherein the fin top hard mask includes a dielectric layer, and wherein a sidewall of the fin top hard mask directly contacts the gate stack, and another sidewall of the fin top hard mask directly contacts the source/drain structure.