公开(公告)号：US11387365B2

公开(公告)日：2022-07-12

申请号：US16837211

申请日：2020-04-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Yen Yu ,  Po-Chi Wu ,  Yueh-Chun Lai

IPC: H01L29/78 ,  H01L21/285 ,  H01L21/3065 ,  H01L21/764 ,  H01L29/06 ,  H01L29/08 ,  H01L29/45 ,  H01L29/66 ,  H01L21/762 ,  H01L29/165 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092

Abstract: In a method of manufacturing a semiconductor device including a Fin FET, a fin structure extending in a first direction is formed over a substrate. An isolation insulating layer is formed over the substrate so that an upper portion of the fin structure is exposed from the isolation insulating layer. A gate structure extending in a second direction crossing the first direction is formed over a part of the fin structure. A fin mask layer is formed on sidewalls of a source/drain region of the fin structure. The source/drain region of the fin structure is recessed. An epitaxial source/drain structure is formed over the recessed fin structure. In the recessing the source/drain region of the fin structure, a plasma process combining etching and deposition processes is used to form a recess having a rounded corner shape in a cross section along the second direction.

公开(公告)号：US20170077302A1

公开(公告)日：2017-03-16

申请号：US14854772

申请日：2015-09-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tung-Wen Cheng ,  Che-Cheng Chang ,  Mu-Tsang Lin ,  Bo-Feng Young ,  Cheng-Yen Yu

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7854

Abstract: The present disclosure relates to a semiconductor device that controls a strain on a channel region by forming a dielectric material in recesses, adjacent to a channel region, in order to provide control over a volume and shape of a strain inducing material of epitaxial source/drain regions formed within the recesses. In some embodiments, the semiconductor device has epitaxial source/drain regions arranged in recesses within an upper surface of a semiconductor body on opposing sides of a channel region. A gate structure is arranged over the channel region, and a dielectric material is arranged laterally between the epitaxial source/drain regions and the channel region. The dielectric material consumes some volume of the recesses, thereby reducing a volume of strain inducing material in epitaxial source/drain regions formed in the recesses.

Abstract translation: 本公开涉及一种半导体器件，其通过在与沟道区相邻的凹槽中形成介电材料来控制沟道区上的应变，以便提供对外延源极/漏极的应变诱导材料的体积和形状的控制 形成在凹部内的区域。 在一些实施例中，半导体器件具有布置在沟道区域的相对侧上的半导体本体的上表面内的凹槽中的外延源极/漏极区域。 栅极结构布置在沟道区域上方，并且电介质材料横向布置在外延源极/漏极区域和沟道区域之间。 电介质材料消耗一些体积的凹槽，从而减少在凹陷中形成的外延源极/漏极区域中的应变诱发材料的体积。

公开(公告)号：US09564528B2

公开(公告)日：2017-02-07

申请号：US14749597

申请日：2015-06-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD

Inventor： Cheng-Yen Yu ,  Che-Cheng Chang ,  Tung-Wen Cheng ,  Zhe-Hao Zhang ,  Bo-Feng Young

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/267 ,  H01L29/08 ,  H01L29/06 ,  H01L29/165 ,  H01L27/088 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L29/7848 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/165 ,  H01L29/267 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for manufacturing a semiconductor device includes forming a fin structure over a substrate. An isolation insulating layer is formed so that an upper part of the fin structure protrudes from the isolation insulating layer. A gate structure is formed over a part of the fin structure. Recesses are formed in the isolation insulating layer at both sides of the fin structure. A recess is formed in a portion of the fin structure which is not covered by the gate structure. The recess in the fin structure and the recesses in the isolation insulating layer are formed such that a depth D1 of the recess in the fin structure and a depth D2 of the recesses in the isolation insulating layer measured from an uppermost surface of the isolation insulating layer satisfy 0≦D1≦D2 (but D1 and D2 are not zero at the same time).

Abstract translation: 一种制造半导体器件的方法包括在衬底上形成翅片结构。 隔离绝缘层形成为使得翅片结构的上部从隔离绝缘层突出。 在鳍结构的一部分上形成栅极结构。 在翅片结构的两侧的隔离绝缘层中形成凹部。 在翅片结构的未被栅极结构覆盖的部分中形成凹部。 翅片结构中的凹部和隔离绝缘层中的凹部被形成为使得翅片结构中的凹部的深度D1和隔离绝缘层中的凹部的深度D2从隔离绝缘层的最上表面测量 满足0≤D1≤D2（但D1和D2同时不为零）。

公开(公告)号：US11043593B2

公开(公告)日：2021-06-22

申请号：US16594237

申请日：2019-10-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Yen Yu ,  Che-Cheng Chang ,  Tung-Wen Cheng ,  Zhe-Hao Zhang ,  Bo-Feng Young

IPC: H01L29/78 ,  H01L29/165 ,  H01L21/02 ,  H01L21/84 ,  H01L27/12 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/267

Abstract: A semiconductor device includes a Fin FET device. The Fin FET device includes a first fin structure extending in a first direction and protruding from an isolation insulating layer, a first gate stack including a first gate electrode layer and a first gate dielectric layer, covering a portion of the first fin structure and extending in a second direction perpendicular to the first direction, and a first source and a first drain, each including a first stressor layer disposed over the first fin structure. The first fin structure and the isolation insulating layer are disposed over a substrate. A height Ha of an interface between the first fin structure and the first stressor layer measured from the substrate is greater than a height Hb of a lowest height of the isolation insulating layer measured from the substrate.

公开(公告)号：US10483394B2

公开(公告)日：2019-11-19

申请号：US16056148

申请日：2018-08-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Yen Yu ,  Che-Cheng Chang ,  Tung-Wen Cheng ,  Zhe-Hao Zhang ,  Bo-Feng Young

IPC: H01L29/78 ,  H01L29/165 ,  H01L21/02 ,  H01L21/84 ,  H01L27/12 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/267

Abstract: A semiconductor device includes a Fin FET device. The Fin FET device includes a first fin structure extending in a first direction and protruding from an isolation insulating layer, a first gate stack including a first gate electrode layer and a first gate dielectric layer, covering a portion of the first fin structure and extending in a second direction perpendicular to the first direction, and a first source and a first drain, each including a first stressor layer disposed over the first fin structure. The first fin structure and the isolation insulating layer are disposed over a substrate. A height Ha of an interface between the first fin structure and the first stressor layer measured from the substrate is greater than a height Hb of a lowest height of the isolation insulating layer measured from the substrate.

公开(公告)号：US10043906B2

公开(公告)日：2018-08-07

申请号：US15402398

申请日：2017-01-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Yen Yu ,  Che-Cheng Chang ,  Tung-Wen Cheng ,  Zhe-Hao Zhang ,  Bo-Feng Young

IPC: H01L29/78 ,  H01L21/8238 ,  H01L29/165 ,  H01L21/02 ,  H01L21/84 ,  H01L27/12 ,  H01L27/092 ,  H01L29/267

Abstract: A semiconductor device includes a Fin FET device. The Fin FET device includes a first fin structure extending in a first direction and protruding from an isolation insulating layer, a first gate stack including a first gate electrode layer and a first gate dielectric layer, covering a portion of the first fin structure and extending in a second direction perpendicular to the first direction, and a first source and a first drain, each including a first stressor layer disposed over the first fin structure. The first fin structure and the isolation insulating layer are disposed over a substrate. A height Ha of an interface between the first fin structure and the first stressor layer measured from the substrate is greater than a height Hb of a lowest height of the isolation insulating layer measured from the substrate.

公开(公告)号：US09991385B2

公开(公告)日：2018-06-05

申请号：US14854772

申请日：2015-09-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tung-Wen Cheng ,  Che-Cheng Chang ,  Mu-Tsang Lin ,  Bo-Feng Young ,  Cheng-Yen Yu

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7854

Abstract: The present disclosure relates to a semiconductor device that controls a strain on a channel region by forming a dielectric material in recesses, adjacent to a channel region, in order to provide control over a volume and shape of a strain inducing material of epitaxial source/drain regions formed within the recesses. In some embodiments, the semiconductor device has epitaxial source/drain regions arranged in recesses within an upper surface of a semiconductor body on opposing sides of a channel region. A gate structure is arranged over the channel region, and a dielectric material is arranged laterally between the epitaxial source/drain regions and the channel region. The dielectric material consumes some volume of the recesses, thereby reducing a volume of strain inducing material in epitaxial source/drain regions formed in the recesses.