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公开(公告)号:US11342458B2
公开(公告)日:2022-05-24
申请号:US17080084
申请日:2020-10-26
发明人: Che-Cheng Chang , Tung-Wen Cheng , Chang-Yin Chen , Mu-Tsang Lin
IPC分类号: H01L21/02 , H01L29/78 , H01L21/306 , H01L21/3105 , H01L21/311 , H01L21/3213 , H01L29/423 , H01L29/08 , H01L29/49 , H01L29/165 , H01L29/66 , H01L29/51
摘要: A semiconductor structure and a method of fabricating the semiconductor structure are provided. The semiconductor structure includes a substrate; a metal gate structure on the substrate; and a spacer next to the metal gate structure having a skirting part extending into the metal gate structure and contacting the substrate. The metal gate structure includes a high-k dielectric layer and a metal gate electrode on the high-k dielectric layer.
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公开(公告)号:US10043906B2
公开(公告)日:2018-08-07
申请号:US15402398
申请日:2017-01-10
发明人: Cheng-Yen Yu , Che-Cheng Chang , Tung-Wen Cheng , Zhe-Hao Zhang , Bo-Feng Young
IPC分类号: H01L29/78 , H01L21/8238 , H01L29/165 , H01L21/02 , H01L21/84 , H01L27/12 , H01L27/092 , H01L29/267
摘要: A semiconductor device includes a Fin FET device. The Fin FET device includes a first fin structure extending in a first direction and protruding from an isolation insulating layer, a first gate stack including a first gate electrode layer and a first gate dielectric layer, covering a portion of the first fin structure and extending in a second direction perpendicular to the first direction, and a first source and a first drain, each including a first stressor layer disposed over the first fin structure. The first fin structure and the isolation insulating layer are disposed over a substrate. A height Ha of an interface between the first fin structure and the first stressor layer measured from the substrate is greater than a height Hb of a lowest height of the isolation insulating layer measured from the substrate.
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公开(公告)号:US09991385B2
公开(公告)日:2018-06-05
申请号:US14854772
申请日:2015-09-15
发明人: Tung-Wen Cheng , Che-Cheng Chang , Mu-Tsang Lin , Bo-Feng Young , Cheng-Yen Yu
CPC分类号: H01L29/7848 , H01L29/66795 , H01L29/785 , H01L29/7851 , H01L29/7854
摘要: The present disclosure relates to a semiconductor device that controls a strain on a channel region by forming a dielectric material in recesses, adjacent to a channel region, in order to provide control over a volume and shape of a strain inducing material of epitaxial source/drain regions formed within the recesses. In some embodiments, the semiconductor device has epitaxial source/drain regions arranged in recesses within an upper surface of a semiconductor body on opposing sides of a channel region. A gate structure is arranged over the channel region, and a dielectric material is arranged laterally between the epitaxial source/drain regions and the channel region. The dielectric material consumes some volume of the recesses, thereby reducing a volume of strain inducing material in epitaxial source/drain regions formed in the recesses.
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公开(公告)号:US11424165B2
公开(公告)日:2022-08-23
申请号:US16654457
申请日:2019-10-16
发明人: Jen-Chun Chou , Tung-Wen Cheng
IPC分类号: H01L21/8234 , H01L29/78 , H01L27/088 , H01L21/762 , H01L29/66
摘要: In a method for manufacturing a semiconductor device, a fin structure is formed over a substrate, an isolation insulating layer is formed over the substrate such that an upper portion of the fin structure protrudes from the isolation insulating layer, a first dielectric layer is formed on the upper portion of the fin structure, a cover layer is formed on the first dielectric layer, the cover layer is partially removed from an upper part of the upper portion of the fin structure with the first dielectric layer, the first dielectric layer is removed from the upper part of the upper portion of the fin structure, a second dielectric layer is formed on the upper part of the upper portion of the fin structure, and a gate electrode is formed on the second dielectric layer and the first dielectric layer disposed on an lower part of the upper portion of the fin structure.
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公开(公告)号:US10770569B2
公开(公告)日:2020-09-08
申请号:US16436753
申请日:2019-06-10
发明人: Wei-Yang Lo , Shih-Hao Chen , Mu-Tsang Lin , Tung-Wen Cheng
IPC分类号: H01L29/66 , H01L29/78 , H01L21/3065 , H01L21/306 , H01L29/08
摘要: A transistor includes a semiconductive fin having a channel portion, a gate stack over the channel portion of the semiconductive fin, source and drain structures on opposite sides of the gate stack and adjoining the semiconductive fin, and a sidewall structure extending along sidewalls of a body portion of the source structure. The source structure has a curved top, and the source structure has a top portion protruding over a top of the sidewall structure.
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公开(公告)号:US10692701B2
公开(公告)日:2020-06-23
申请号:US15460771
申请日:2017-03-16
发明人: Chang-Yin Chen , Tung-Wen Cheng , Che-Cheng Chang , Jr-Jung Lin , Chih-Han Lin
IPC分类号: H01L21/8234 , H01J37/32 , H01L21/3213 , H01L29/66 , H01L29/78 , H01L21/67
摘要: A dry etching apparatus includes a process chamber, a stage, a gas supply device and a plasma generating device. The stage is in the process chamber and is configured to support a wafer, wherein the wafer has a center region and a periphery region surrounding the center region. The gas supply device is configured to supply a first flow of an etching gas to the center region and supply a second flow of the etching gas to the periphery region. The plasma generating device is configured to generate plasma from the etching gas.
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公开(公告)号:US10164109B2
公开(公告)日:2018-12-25
申请号:US14609088
申请日:2015-01-29
IPC分类号: H01L27/088 , H01L21/8234 , H01L29/78 , H01L29/66 , H01L21/762 , H01L21/306 , H01L29/08 , H01L29/165 , H01L21/311
摘要: A fin field effect transistor (FinFET) device structure and method for forming the FinFET device structure are provided. The FinFET structure includes a substrate, and the substrate includes a core region and an I/O region. The FinFET structure includes a first etched fin structure formed in the core region, and a second etched fin structure formed in the I/O region. The FinFET structure further includes a plurality of gate stack structures formed over the first etched fin structure and the second etched fin structure, and a width of the first etched fin structure is smaller than a width of the second etched fin structure.
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公开(公告)号:US09653605B2
公开(公告)日:2017-05-16
申请号:US14517310
申请日:2014-10-17
IPC分类号: H01L29/78 , H01L29/08 , H01L29/66 , H01L29/06 , H01L21/762 , H01L21/306 , H01L29/165
CPC分类号: H01L29/7851 , H01L21/30604 , H01L21/31116 , H01L21/76224 , H01L21/823412 , H01L21/823431 , H01L21/823481 , H01L27/0886 , H01L29/0847 , H01L29/165 , H01L29/6653 , H01L29/66795 , H01L29/7848
摘要: A fin field effect transistor (FinFET) device structure and method for forming FinFET device structure are provided. The FinFET structure includes a substrate and a fin structure extending above the substrate. The FinFET structure includes an epitaxial structure formed on the fin structure, and the epitaxial structure has a first height. The FinFET structure also includes fin sidewall spacers formed adjacent to the epitaxial structure. The sidewall spacers have a second height and the first height is greater than the second height, and the fin sidewall spacers are configured to control a volume and the first height of the epitaxial structure.
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公开(公告)号:US09564528B2
公开(公告)日:2017-02-07
申请号:US14749597
申请日:2015-06-24
发明人: Cheng-Yen Yu , Che-Cheng Chang , Tung-Wen Cheng , Zhe-Hao Zhang , Bo-Feng Young
IPC分类号: H01L29/78 , H01L29/66 , H01L29/267 , H01L29/08 , H01L29/06 , H01L29/165 , H01L27/088 , H01L21/02 , H01L21/8234 , H01L21/84 , H01L27/12
CPC分类号: H01L29/7848 , H01L21/02529 , H01L21/02532 , H01L21/0262 , H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L21/845 , H01L27/0924 , H01L27/1211 , H01L29/165 , H01L29/267 , H01L29/66795 , H01L29/785
摘要: A method for manufacturing a semiconductor device includes forming a fin structure over a substrate. An isolation insulating layer is formed so that an upper part of the fin structure protrudes from the isolation insulating layer. A gate structure is formed over a part of the fin structure. Recesses are formed in the isolation insulating layer at both sides of the fin structure. A recess is formed in a portion of the fin structure which is not covered by the gate structure. The recess in the fin structure and the recesses in the isolation insulating layer are formed such that a depth D1 of the recess in the fin structure and a depth D2 of the recesses in the isolation insulating layer measured from an uppermost surface of the isolation insulating layer satisfy 0≦D1≦D2 (but D1 and D2 are not zero at the same time).
摘要翻译: 一种制造半导体器件的方法包括在衬底上形成翅片结构。 隔离绝缘层形成为使得翅片结构的上部从隔离绝缘层突出。 在鳍结构的一部分上形成栅极结构。 在翅片结构的两侧的隔离绝缘层中形成凹部。 在翅片结构的未被栅极结构覆盖的部分中形成凹部。 翅片结构中的凹部和隔离绝缘层中的凹部被形成为使得翅片结构中的凹部的深度D1和隔离绝缘层中的凹部的深度D2从隔离绝缘层的最上表面测量 满足0≤D1≤D2(但D1和D2同时不为零)。
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公开(公告)号:US11594534B2
公开(公告)日:2023-02-28
申请号:US17313590
申请日:2021-05-06
发明人: Tung-Wen Cheng , Chih-Shan Chen , Mu-Tsang Lin
IPC分类号: H01L27/088 , H01L29/417 , H01L29/66 , H01L29/78 , H01L21/8234 , H01L23/528 , H01L29/06
摘要: A semiconductor device includes a semiconductor substrate, a plurality of semiconductor fins, a gate stack and an epitaxy structure. The semiconductor fins are present on the semiconductor substrate. The semiconductor fins respectively include recesses therein. The gate stack is present on portions of the semiconductor fins that are adjacent to the recesses. The epitaxy structure is present across the recesses of the semiconductor fins. The epitaxy structure includes a plurality of corners and at least one groove present between the corners, and the groove has a curvature radius greater than that of at least one of the corners.
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