公开(公告)号：US11670551B2

公开(公告)日：2023-06-06

申请号：US16926528

申请日：2020-07-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Chi Yang ,  Allen Chien ,  Cheng-Ting Ding ,  Chien-Chih Lin ,  Chien-Chih Lee ,  Shih-Hao Lin ,  Tsung-Hung Lee ,  Chih Chieh Yeh ,  Po-Kai Hsiao ,  Tsai-Yu Huang

IPC: H01L21/8234 ,  H01L21/324 ,  H01L29/78 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L21/823431 ,  H01L21/823412 ,  H01L21/823418 ,  H01L29/0607 ,  H01L29/1054

Abstract: The present disclosure provides methods of fabricating a semiconductor device. A method according to one embodiment includes forming, on a substrate, a first fin formed of a first semiconductor material and a second fin formed of a second semiconductor material different from the first semiconductor material, forming a semiconductor cap layer over the first fin and the second fin, and annealing the semiconductor cap layer at a first temperature while at least a portion of the semiconductor cap layer is exposed.

公开(公告)号：US20240387274A1

公开(公告)日：2024-11-21

申请号：US18786886

申请日：2024-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Chi Yang ,  Allen Chien ,  Tsai-Yu Huang ,  Chien-Chih Lin ,  Po-Kai Hsiao ,  Shih-Hao Lin ,  Chien-Chih Lee ,  Chih Chieh Yeh ,  Cheng-Ting Ding ,  Tsung-Hung Lee

IPC: H01L21/8234 ,  H01L29/06 ,  H01L29/10

Abstract: A method according to the present disclosure includes providing a workpiece including a first fin-shaped structure and a second fin-shaped structure over a substrate, depositing a nitride liner over the substrate and sidewalls of the first fin-shaped structure and the second fin-shaped structure, forming an isolation feature over the nitride liner and between the first fin-shaped structure and the second fin-shaped structure, epitaxially growing a cap layer on exposed surfaces of the first fin-shaped structure and the second fin-shaped structure and above the nitride liner, crystalizing the cap layer, and forming a first source/drain feature over a first source/drain region of the first fin-shaped structure and a second source/drain feature over a second source/drain region of the second fin-shaped structure.

公开(公告)号：US09620500B2

公开(公告)日：2017-04-11

申请号：US15158462

申请日：2016-05-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chin-Chi Wang ,  Chien-Chih Lee ,  Tien-Wei Chiang ,  Ching-Wei Tsai ,  Chih-Ching Wang ,  Jon-Hsu Ho ,  Wen-Hsing Hsieh

IPC: H01L29/66 ,  H01L21/336 ,  H01L27/088 ,  H01L29/78 ,  H01L29/45 ,  H01L29/06 ,  H01L23/528 ,  H01L21/283 ,  H01L21/306 ,  H01L21/768 ,  H01L21/31 ,  H01L21/8234 ,  H01L29/423

CPC classification number: H01L27/088 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/31 ,  H01L21/76897 ,  H01L21/823487 ,  H01L23/528 ,  H01L29/0649 ,  H01L29/42356 ,  H01L29/45 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7845 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A series-connected transistor structure includes a first source, a first channel-drain structure, a second channel-drain structure, a gate dielectric layer, a gate, a first drain pad and a second drain pad. The first source is over a substrate. The first channel-drain structure is over the first source and includes a first channel and a first drain thereover. The second channel-drain structure is over the first source and substantially parallel to the first channel-drain structure and includes a second channel and a second drain thereover. The gate dielectric layer surrounds the first channel and the second channel. The gate surrounds the gate dielectric layer. The first drain pad is over and in contact with the first drain. The second drain pad is over and in contact with the second drain, in which the first drain pad and the second drain pad are separated from each other.

公开(公告)号：US20210098305A1

公开(公告)日：2021-04-01

申请号：US16926528

申请日：2020-07-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Chi Yang ,  Allen Chien ,  Cheng-Ting Ding ,  Chien-Chih Lin ,  Chien-Chih Lee ,  Shih-Hao Lin ,  Tsung-Hung Lee ,  Chih Chieh Yeh ,  Po-Kai Hsiao ,  Tsai-Yu Huang

IPC: H01L21/8234 ,  H01L29/06 ,  H01L29/10

Abstract: The present disclosure provides methods of fabricating a semiconductor device. A method according to one embodiment includes forming, on a substrate, a first fin formed of a first semiconductor material and a second fin formed of a second semiconductor material different from the first semiconductor material, forming a semiconductor cap layer over the first fin and the second fin, and annealing the semiconductor cap layer at a first temperature while at least a portion of the semiconductor cap layer is exposed.

公开(公告)号：US20230326802A1

公开(公告)日：2023-10-12

申请号：US18329396

申请日：2023-06-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Szu-Chi Yang ,  Allen Chien ,  Tsai-Yu Huang ,  Chien-Chih Lin ,  Po-Kai Hsiao ,  Shih-Hao Lin ,  Chien-Chih Lee ,  Chih Chieh Yeh ,  Cheng-Ting Ding ,  Tsung-Hung Lee

IPC: H01L21/8234 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L21/823431 ,  H01L29/0607 ,  H01L21/823418 ,  H01L21/823412 ,  H01L29/1054

Abstract: The present disclosure provides methods of fabricating a semiconductor device. A method according to one embodiment includes forming, on a substrate, a first fin formed of a first semiconductor material and a second fin formed of a second semiconductor material different from the first semiconductor material, forming a semiconductor cap layer over the first fin and the second fin, and annealing the semiconductor cap layer at a first temperature while at least a portion of the semiconductor cap layer is exposed.

公开(公告)号：US09373620B2

公开(公告)日：2016-06-21

申请号：US14485541

申请日：2014-09-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chin-Chi Wang ,  Chien-Chih Lee ,  Tien-Wei Chiang ,  Ching-Wei Tsai ,  Chih-Ching Wang ,  Jon-Hsu Ho ,  Wen-Hsing Hsieh

IPC: H01L29/66 ,  H01L21/336 ,  H01L27/088 ,  H01L29/78 ,  H01L29/45 ,  H01L29/06 ,  H01L23/528 ,  H01L21/283 ,  H01L21/306 ,  H01L21/768 ,  H01L21/31

CPC classification number: H01L27/088 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/31 ,  H01L21/76897 ,  H01L21/823487 ,  H01L23/528 ,  H01L29/0649 ,  H01L29/42356 ,  H01L29/45 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7845 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A series-connected transistor structure includes a first source, a first channel-drain structure, a second channel-drain structure, a gate dielectric layer, a gate, a first drain pad and a second drain pad. The first source is over a substrate. The first channel-drain structure is over the first source and includes a first channel and a first drain thereover. The second channel-drain structure is over the first source and substantially parallel to the first channel-drain structure and includes a second channel and a second drain thereover. The gate dielectric layer surrounds the first channel and the second channel. The gate surrounds the gate dielectric layer. The first drain pad is over and in contact with the first drain. The second drain pad is over and in contact with the second drain, in which the first drain pad and the second drain pad are separated from each other.

Abstract translation: 串联连接的晶体管结构包括第一源极，第一沟道 - 漏极结构，第二沟道 - 漏极结构，栅极电介质层，栅极，第一漏极焊盘和第二漏极焊盘。 第一个来源是在一个基板上。 第一沟道 - 漏极结构在第一源极上并且包括第一沟道和第一漏极。 第二沟道 - 漏极结构在第一源极上并且基本上平行于第一沟道 - 漏极结构并且包括第二沟道和第二漏极。 栅介质层围绕第一通道和第二通道。 栅极围绕栅介质层。 第一个漏极焊盘是与第一个漏极接触的。 第二漏极焊盘与第二漏极接触，其中第一漏极焊盘和第二漏极焊盘彼此分离。