公开(公告)号：US20230402429A1

公开(公告)日：2023-12-14

申请号：US18151758

申请日：2023-01-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Fu Tseng ,  Yu Chieh Yung ,  Cheng-Hsien Hsieh ,  Hung-Pin Chang ,  Li-Han Hsu ,  Wei-Cheng Wu ,  Der-Chyang Yeh

IPC: H01L25/065 ,  H01L25/10 ,  H01L23/498 ,  H01L23/48 ,  H01L21/48 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L25/0655 ,  H01L25/105 ,  H01L23/49833 ,  H01L23/481 ,  H01L21/486 ,  H01L23/5383 ,  H01L24/20 ,  H01L24/19 ,  H01L24/16 ,  H01L24/32 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L24/73 ,  H01L2224/73204 ,  H01L2224/0557 ,  H01L2224/214 ,  H01L2224/19

Abstract: Manufacturing flexibility and efficiency are obtained with a method, and resulting structure, in which RDL contact features can be formed and aligned to through silicon vias (TSV's) regardless of any potential mismatch in the respective critical dimensions (CD's) between the manufacturing process for forming the TSV's and the manufacturing process for forming the contact features. Various processes for a self-aligned exposure of the underlying TSV's, without the need for additional photolithography steps are provided.