公开(公告)号：US20230073062A1

公开(公告)日：2023-03-09

申请号：US17988432

申请日：2022-11-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jui-Chieh CHEN ,  Tsung-Chih CHIEN ,  Chih-Tsung SHIH ,  Tsung-Chuan LEE

IPC: G03F7/20 ,  G03F1/66

Abstract: A method for preventing photomask contamination includes securing a photomask on a bottom surface of an electrostatic chuck; generating a first voltage at a peripheral area of the bottom surface of the electrostatic chuck to attract a particle onto the peripheral area of the bottom surface of the electrostatic chuck, wherein the peripheral area of the bottom surface of the electrostatic chuck is not directly above the photomask; after generating the first voltage, generating a second voltage at the peripheral area of the bottom surface of the electrostatic chuck to repulse the particle, wherein the first voltage and the second voltage have opposite electrical properties; and generating a third voltage, by using a collecting plate, near a sidewall of the photomask to attract the repulsed particle.

公开(公告)号：US20210389661A1

公开(公告)日：2021-12-16

申请号：US16900384

申请日：2020-06-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Tsung SHIH ,  Yu-Hsun WU ,  Bo-Tsun LIU ,  Tsung-Chuan LEE

IPC: G03F1/22 ,  G03F7/20

Abstract: A method of forming an extreme ultraviolet (EUV) mask includes forming a multilayer Mo/Si stack comprising alternating stacked Mo and Si layers over a mask substrate; forming a ruthenium capping layer over the multilayer Mo/Si stack; doping the ruthenium capping layer with a halogen element, a pentavalent element, a hexavalent element or combinations thereof; forming an absorber layer over the ruthenium capping layer; and etching the absorber layer to form a pattern in the absorber layer.

公开(公告)号：US20200150550A1

公开(公告)日：2020-05-14

申请号：US16740756

申请日：2020-01-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Zi-Wen CHEN ,  Po-Chung CHENG ,  Chih-Tsung SHIH ,  Li-Jui CHEN ,  Shih-Chang SHIH

IPC: G03F7/20 ,  G03F9/00 ,  G01M11/02 ,  G01B11/27

Abstract: Embodiments described herein provide a method for cleaning contamination from sensors in a lithography tool without requiring recalibrating the lithography tool. More particularly, embodiments described herein teach cleaning the sensors using hydrogen radicals for a short period while the performance drifting is still above the drift tolerance. After a cleaning process described herein, the lithography tool can resume production without recalibration.

公开(公告)号：US20240361533A1

公开(公告)日：2024-10-31

申请号：US18769241

申请日：2024-07-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Tsung SHIH ,  Chewn-Pu JOU ,  Stefan RUSU ,  Felix Ying-Kit TSUI ,  Lan-Chou CHO

IPC: G02B6/34 ,  G02B6/30

CPC classification number: G02B6/34 ,  G02B6/305

Abstract: Disclosed are apparatus and methods for optical coupling. In one example, a method for forming an optical coupler, includes: forming an insulation layer on a semiconductor substrate; epitaxially growing a semiconductor material on the insulation layer to form a semiconductor layer; etching, according to a predetermined pattern, the semiconductor layer to form: an array of etched holes in the semiconductor layer to form a grating region, a first taper structure extending from a first side of the grating region, wherein a shape of the first taper structure in the semiconductor layer is a first triangle that is asymmetric about any line perpendicular to the first side of the grating region, and a second taper structure extending from a second side of the grating region, wherein a shape of the second taper structure in the semiconductor layer is a second triangle that is asymmetric about any line perpendicular to the second side of the grating region, wherein the first side and the second side are substantially perpendicular to each other; and depositing a dielectric material into the array of etched regions to form an array of scattering elements in the semiconductor layer, wherein the scattering elements are arranged to form a two-dimensional (2D) grating.

公开(公告)号：US20210191283A1

公开(公告)日：2021-06-24

申请号：US16885149

申请日：2020-05-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Wei LEE ,  Jui-Chieh CHEN ,  Chih-Tsung SHIH ,  Tsung-Chuan LEE

IPC: G03F7/20 ,  H01L21/027 ,  H01L21/677

Abstract: In accordance with some embodiments, a method for processing a semiconductor wafer is provided. The method includes transporting a carrier along with a reticle supported by the carrier in a lithography exposure apparatus. The method also includes regulating particles in the carrier through a magnetic field. In addition, the method includes removing the reticle from the carrier. The method further includes performing, using the reticle, a lithography exposure process to the semiconductor wafer in the lithography exposure apparatus.

公开(公告)号：US20200073225A1

公开(公告)日：2020-03-05

申请号：US16530218

申请日：2019-08-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Tsung SHIH ,  Tsung-Chih CHIEN ,  Shih-Chi FU ,  Chi-Hua FU ,  Kuotang CHENG ,  Bo-Tsun LIU ,  Tsung Chuan LEE

IPC: G03F1/22 ,  G03F1/38

Abstract: An extreme ultraviolet (EUV) mask includes a multilayer Mo/Si stack comprising alternating Mo and Si layers disposed over a first major surface of a mask substrate, a capping layer made of ruthenium (Ru) disposed over the multilayer Mo/Si stack, and an absorber layer on the capping layer. The EUV mask includes a circuit pattern area and a particle attractive area, and the capping layer is exposed at bottoms of patterns in the particle attractive area.

公开(公告)号：US20200350306A1

公开(公告)日：2020-11-05

申请号：US16933127

申请日：2020-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Wen CHO ,  Fu-Jye LIANG ,  Chun-Kuang CHEN ,  Chih-Tsung SHIH ,  Li-Jui CHEN ,  Po-Chung CHENG ,  Chin-Hsiang LIN

IPC: H01L27/02 ,  G03F1/36 ,  G06F30/30 ,  G06F30/39

Abstract: A layout modification method for fabricating a semiconductor device is provided. Uniformity of critical dimensions of a first portion and a second portion in a patterned layer are calculated by using a layout for an exposure manufacturing process to produce the semiconductor device. A width of the second portion equals a penumbra size of the exposure manufacturing process, and the penumbra size is utilized to indicate which area of the patterned layer is affected by light leakage exposure from another exposure manufacturing process. Non-uniformity between the first and second portions of the patterned layer is compensated according to the uniformity of critical dimensions to generate a modified layout. The patterned layer includes a plurality of absorbers, and a first width of the absorbers is the first portion is less than a second width of the absorbers in the second portion the second portion.

公开(公告)号：US20200348586A1

公开(公告)日：2020-11-05

申请号：US16927131

申请日：2020-07-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Wen CHO ,  Fu-Jye LIANG ,  Chun-Kuang CHEN ,  Chih-Tsung SHIH ,  Li-Jui CHEN ,  Po-Chung CHENG ,  Chin-Hsiang LIN

IPC: G03F1/36 ,  G03F1/22 ,  G03F1/44

Abstract: A method for collecting information in image-error compensation is provided. The method includes providing a reticle having a first image structure and a second image structure; moving a light shading member to control a first exposure field; projecting a light over the first exposure field; recording an image of the first image structure after the light is projected; moving the light shading member to control a second exposure field; projecting the light over the second exposure field; and recording an image of the second image structure after the light is projected.

公开(公告)号：US20200057383A1

公开(公告)日：2020-02-20

申请号：US16540874

申请日：2019-08-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Tsung SHIH ,  Bo-Tsun LIU ,  Tsung Chuan LEE

IPC: G03F7/20 ,  G01N15/12 ,  G03F1/84 ,  G03F1/00 ,  G03F1/62

Abstract: An extreme ultraviolet (EUV) lithography system includes an extreme ultraviolet (EUV) radiation source to emit EUV radiation, a collector for collecting the EUV radiation and focusing the EUV radiation, a reticle stage for supporting a reticle including a pellicle for exposure to the EUV radiation, and at least one sensor configured to detect particles generated due to breakage of the pellicle.

公开(公告)号：US20190131290A1

公开(公告)日：2019-05-02

申请号：US15797842

申请日：2017-10-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Wen CHO ,  Fu-Jye LIANG ,  Chun-Kuang CHEN ,  Chih-Tsung SHIH ,  Li-Jui CHEN ,  Po-Chung CHENG ,  Chin-Hsiang LIN

IPC: H01L27/02 ,  G06F17/50

CPC classification number: H01L27/0207 ,  G06F17/5009 ,  G06F17/5045 ,  G06F17/5068 ,  G06F2217/12 ,  H01L27/0203

Abstract: A layout modification method for fabricating an integrated circuit is provided. The layout modification method includes calculating uniformity of critical dimension of a patterned layer with a layout for an exposure manufacturing process to produce a semiconductor device. The patterned layer is divided into a first portion and a second portion which is adjacent to the first portion, and a width of the second portion equals to a penumbra size of the exposure manufacturing process. The layout modification method further includes retrieving an adjusting parameter for modifying the layout of the semiconductor device; determining a compensation amount based on the adjusting parameter and the uniformity of critical dimension; and compensating the critical dimension of the second portion of the patterned layer by utilizing the compensation amount to generate a modified layout.