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    SEMICONDUCTOR DEVICE AND LAYOUT THEREOF
    2.
    发明申请
    SEMICONDUCTOR DEVICE AND LAYOUT THEREOF 有权

    公开(公告)号：US20210082904A1

    公开(公告)日：2021-03-18

    申请号：US17107311

    申请日：2020-11-30

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Cheng-I HUANG ,  Ting-Wei CHIANG ,  Shih-Chi FU ,  Sheng-Fang CHENG ,  Jung-Chan YANG

    IPC: H01L27/02 ,  G06F30/39 ,  H01L27/088 ,  H01L29/66

    Abstract: A semiconductor device includes a first fin, a first continuous fin and continuous gates. The first fin is formed on a substrate, and includes first and second portions that are spaced apart by a first recess. A side of the first portion and a side of the second portion are located at two sides of the first recess, respectively. The first continuous fin is formed on the substrate, and extends along the first portion, the first recess and the second portion. The continuous gates are formed on the substrate, and arranged to intersect the first continuous fin and the first fin in a layout view. A first number of the continuous gates are disposed across the first recess and each of the first number of the continuous gates is disposed between the two sides of the first recess in a layout view. A method is also disclosed herein.

    SEMICONDUCTOR DEVICE AND LAYOUT THEREOF
    6.
    发明申请
    SEMICONDUCTOR DEVICE AND LAYOUT THEREOF 有权

    公开(公告)号：US20240395795A1

    公开(公告)日：2024-11-28

    申请号：US18791291

    申请日：2024-07-31

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Cheng-I HUANG ,  Ting-Wei CHIANG ,  Shih-Chi FU ,  Sheng-Fang CHENG ,  Jung-Chan YANG

    IPC: H01L27/02 ,  G06F30/39 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66

    Abstract: A semiconductor device includes a first fin, a first continuous fin and continuous gates. The first fin is formed on a substrate, and includes first and second portions that are spaced apart by a first recess. A side of the first portion and a side of the second portion are located at two sides of the first recess, respectively. The first continuous fin is formed on the substrate, and extends along the first portion, the first recess and the second portion. The continuous gates are formed on the substrate, and arranged to intersect the first continuous fin and the first fin in a layout view. A first number of the continuous gates are disposed across the first recess and each of the first number of the continuous gates is disposed between the two sides of the first recess in a layout view. A method is also disclosed herein.

    SEMICONDUCTOR DEVICE AND LAYOUT THEREOF
    7.
    发明申请
    SEMICONDUCTOR DEVICE AND LAYOUT THEREOF 审中-公开

    公开(公告)号：US20190103393A1

    公开(公告)日：2019-04-04

    申请号：US16206746

    申请日：2018-11-30

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Cheng-I HUANG ,  Ting-Wei CHIANG ,  Shih-Chi FU ,  Sheng-Fang CHENG ,  Jung-Chan YANG

    IPC: H01L27/02 ,  G06F17/50 ,  H01L29/66 ,  H01L27/088

    Abstract: A method includes the operations below. A first and second layout patterns corresponding to a first and second area are placed. Third layout patterns corresponding to a first continuous fin over the first area and second area, and corresponding to a second fin including separate portions spaced apart by a first recess over the first area are placed. A fourth layout pattern, corresponding to a dummy gate, at the recess portion and between the first layout pattern and the second layout pattern, is placed to generate a layout design of a semiconductor device. A side of the second area facing the first recess is substantially flat, and the semiconductor device is fabricated by a tool based on the layout design. A first length of the first continuous fin is equal to a sum of a second length of the second fin and a third length of the first recess.

    FIELD EFFECT TRANSISTOR WITH ISOLATION STRUCTURE AND RELATED METHOD
    8.
    发明申请
    FIELD EFFECT TRANSISTOR WITH ISOLATION STRUCTURE AND RELATED METHOD 有权

    公开(公告)号：US20240395813A1

    公开(公告)日：2024-11-28

    申请号：US18498334

    申请日：2023-10-31

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chih-Hsiung PENG ,  Shih-Chi FU ,  Kuei-Shun CHEN ,  Te-Yu CHEN

    IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

    Abstract: A method includes: forming a first stack of semiconductor channels and a second stack of semiconductor channels over a substrate, the first stack being adjacent the second stack, a transition region overlapping neighboring protruding corners of the first stack and the second stack; forming a plurality of sacrificial gates over the first stack and the second stack, the plurality of sacrificial gates extending in a first direction and being arranged along a second direction transverse the first direction based on a first pitch along a second direction, each of the plurality of sacrificial gates having a first width; simultaneously with the forming a plurality of sacrificial gates, forming a bar structure over the transition region and adjacent to the plurality of sacrificial gates, the bar structure having a second width that exceeds a sum of the first pitch and the first width; forming a plurality of source/drain openings in areas of the first and second stacks of semiconductor channels that are exposed by the plurality of sacrificial gates and the bar structure; forming a plurality of source/drain regions in the plurality of source/drain openings; replacing the plurality of sacrificial gates with a plurality of gate structures that wrap around the semiconductor channels of the first and second stacks; simultaneously with replacing the plurality of sacrificial gates, replacing the bar structure with an inactive gate structure; and replacing the inactive gate structure with an isolation structure.

    METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
    10.
    发明申请
    METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20200058762A1

    公开(公告)日：2020-02-20

    申请号：US16507951

    申请日：2019-07-10

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Chi-Wen HSIEH ,  Chien-Ping HUNG ,  Chi-Kang CHANG ,  Shih-Chi FU ,  Kuei-Shun CHEN

    IPC: H01L29/66 ,  H01L29/78

    Abstract: In a method of manufacturing a semiconductor device, a layout is prepared. The layout includes active region patterns, each of the active region patterns corresponding to one or two fin structures, first fin cut patterns and second fin cut patterns. At least one pattern selected from the group consisting of the first fin cut patterns and the second fin cut patterns has a non-rectangular shape. The layout is modified by adding one or more dummy active region patterns and by changing the at least one pattern to be a rectangular pattern. Base fin structures are formed according to a modified layout including the active region patterns and the dummy active region patterns. Part of the base fin structures is removed according to one of a modified layout of the first fin cut patterns and a modified layout of the second fin cut patterns.

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