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公开(公告)号：US20210082903A1
公开(公告)日：2021-03-18
申请号：US17092100
申请日：2020-11-06
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Charles Chew-Yuen YOUNG , Chih-Liang CHEN , Chih-Ming LAI , Jiann-Tyng TZENG , Shun-Li CHEN , Kam-Tou SIO , Shih-Wei PENG , Chun-Kuang CHEN , Ru-Gun LIU
IPC: H01L27/02 , H01L21/768 , H01L21/8234 , H01L23/485 , G06F30/394
Abstract: A method is disclosed, including the following operations: arranging a first gate structure extending continuously above a first active region and a second active region of a substrate; arranging a first separation spacer disposed on the first gate structure to isolate an electronic signal transmitted through a first gate via and a second gate via that are disposed on the first gate structure, in which the first gate via and the second gate via are arranged above the first active region and the second active region respectively; and arranging a first local interconnect between the first active region and the second active region, in which the first local interconnect is electrically coupled to a first contact disposed on the first active region and a second contact disposed on the second active region.
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公开(公告)号：US20200264515A1
公开(公告)日：2020-08-20
申请号：US16866188
申请日：2020-05-04
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Hung-Wen CHO , Fu-Jye LIANG , Chun-Kuang CHEN , Chih-Tsung SHIH , Li-Jui CHEN , Po-Chung CHENG , Chin-Hsiang LIN
IPC: G03F7/20
Abstract: A method of controlling reticle masking blade positioning to minimize the impact on critical dimension uniformity includes determining a target location of a reticle masking blade relative to a reflective reticle and positioning the reticle masking blade at the target location. A position of the reticle masking blade is monitored during an imaging operation. The position of the reticle masking blade is compared with the target location and the position of the reticle masking blade is adjusted if the position of the reticle masking blade is outside a tolerance of the target location.
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公开(公告)号：US20160172297A1
公开(公告)日：2016-06-16
申请号：US15050087
申请日：2016-02-22
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Chih-Liang CHEN , Chih-Ming LAI , Yung-Sung YEN , Kam-Tou SIO , Tsong-Hua OU , Chun-Kuang CHEN , Ru-Gun LIU , Shu-Hui SUNG , Charles Chew-Yuen YOUNG
IPC: H01L23/528 , H01L27/118 , H01L27/02 , H01L23/522
CPC classification number: H01L23/528 , H01L23/5226 , H01L27/0207 , H01L27/11803 , H01L2924/0002 , H01L2924/00
Abstract: Semiconductor structures are provided. The semiconductor structure includes a plurality of gate structures extending in a first direction formed over a substrate. The gate structures follow the following equation: 0.2 P gate min + 0.35 L gate min + 0.3 H gate min - 20 0.2 L gate min + 0.8 H gate min - 5 × 0.3 L gate min + 0.3 H gate min + 5 38 ≤ 0.32 Pgate min is the minimum value among gate pitches of the gate structures, and Lgate min is the minimum value among gate lengths of the gate structures. Hgate min is the minimum value among gate heights of the gate structures.
Abstract translation: 提供半导体结构。 半导体结构包括沿着形成在衬底上的第一方向延伸的多个栅极结构。 门结构遵循以下公式：0.2P门min + 0.35min min min min 最小 - 5×0.3英尺L门槛最小+ 0.3H门min + 5 38≤0.32 Pgate min是栅极结构的栅间距中的最小值，Lgate min是 栅极结构的栅极长度。 Hgate min是门结构栅极高度的最小值。
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公开(公告)号：US20190163046A1
公开(公告)日：2019-05-30
申请号：US16151300
申请日：2018-10-03
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Hung-Wen CHO , Fu-Jye LIANG , Chun-Kuang CHEN , Chih-Tsung SHIH , Li-Jui CHEN , Po-Chung CHENG , Chin-Hsiang LIN
Abstract: A method of controlling reticle masking blade positioning to minimize the impact on critical dimension uniformity includes determining a target location of a reticle masking blade relative to a reflective reticle and positioning the reticle masking blade at the target location. A position of the reticle masking blade is monitored during an imaging operation. The position of the reticle masking blade is compared with the target location and the position of the reticle masking blade is adjusted if the position of the reticle masking blade is outside a tolerance of the target location.
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公开(公告)号：US20190137866A1
公开(公告)日：2019-05-09
申请号：US15906586
申请日：2018-02-27
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Hung-Wen CHO , Fu-Jye LIANG , Chun-Kuang CHEN , Chih-Tsung SHIH , Li-Jui CHEN , Po-Chung CHENG , Chin-Hsiang LIN
Abstract: A reticle used for collecting information for image-error compensation is provided. The reticle includes a first black border structure and a second black border structure formed over a substrate. The first and second black borders are concentric with a center of the substrate. The reticle further includes a first image structure and a second image structure formed over the substrate. The first and second image structures each has patterns representing features to be patterned on a semiconductor wafer. In a direction away from the center of the substrate, the second image structure, the second black border structure, the first image structure and the first black border structure are arranged in order.
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Patent Agency Ranking
公开(公告)号：US20180335706A1
公开(公告)日：2018-11-22
申请号：US15597897
申请日：2017-05-17
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Chung-Cheng WANG , Chun-Kuang CHEN , Chia-Cheng CHAO
IPC: G03F7/20
CPC classification number: G03F7/70875 , G03F7/70991 , H01L21/67109
Abstract: In a pattern forming method, a resist layer disposed on a wafer is exposed by an energy beam. A post-exposure-bake (PEB) is performed on the wafer with the exposed resist layer by using a PEB apparatus. After the PEB, the exposed resist layer is developed, thereby forming a resist pattern. The PEB apparatus includes a baking plate, and the wafer is placed on the baking plate for the PEB when a temperature of the wafer is within a predetermined temperature range.
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公开(公告)号：US20240096867A1
公开(公告)日：2024-03-21
申请号：US18526395
申请日：2023-12-01
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Charles Chew-Yuen YOUNG , Chih-Liang CHEN , Chih-Ming LAI , Jiann-Tyng TZENG , Shun-Li CHEN , Kam-Tou SIO , Shih-Wei PENG , Chun-Kuang CHEN , Ru-Gun LIU
IPC: H01L27/02 , G06F30/394 , H01L21/768 , H01L21/8234 , H01L23/485
CPC classification number: H01L27/0207 , G06F30/394 , H01L21/76895 , H01L21/823418 , H01L21/823425 , H01L21/823431 , H01L21/823437 , H01L21/823475 , H01L23/485 , H01L23/528
Abstract: A semiconductor structure is provided and includes a first gate structure, a second gate structure, and at least one local interconnect that extend continuously across a non-active region from a first active region to a second active region. The semiconductor structure further includes a first separation spacer disposed on the first gate structure and first vias on the first gate structure. The first vias are arranged on opposite sides of the first separation spacer are isolated from each other and apart from the first separation spacer by different distances.
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公开(公告)号：US20190123036A1
公开(公告)日：2019-04-25
申请号：US16216843
申请日：2018-12-11
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Charles Chew-Yuen YOUNG , Chih-Liang CHEN , Chih-Ming LAI , Jiann-Tyng TZENG , Shun-Li CHEN , Kam-Tou SIO , Shih-Wei PENG , Chun-Kuang CHEN , Ru-Gun LIU
IPC: H01L27/02 , H01L21/768 , H01L21/8234 , G06F17/50 , H01L23/485
Abstract: Gate structures extending continuously above a first active region, a second active region and a non-active region of a substrate of a semiconductor structure are arranged. At least one local interconnect over the non-active region and between two of the gate structures is selectively arranged, to couple at least one of contacts that is arranged above the first active region to at least one of the contacts that is arranged above the second active region.
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公开(公告)号：US20190104604A1
公开(公告)日：2019-04-04
申请号：US16132990
申请日：2018-09-17
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Shang-Chieh CHIEN , Chi YANG , Jen-Yang CHUNG , Shao-Wei LUO , Tzung-Chi FU , Chun-Kuang CHEN , Li-Jui CHEN , Po-Chung CHENG
Abstract: An extreme ultraviolet (EUV) source includes a collector mirror, a drain, a droplet generator configured to eject a target material toward the drain, a pellicle disposed over the collector mirror. The pellicle is configured to catch debris formed of the target material.
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公开(公告)号：US20230187434A1
公开(公告)日：2023-06-15
申请号：US18167651
申请日：2023-02-10
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Charles Chew-Yuen YOUNG , Chih-Liang CHEN , Chih-Ming LAI , Jiann-Tyng TZENG , Shun-Li CHEN , Kam-Tou SIO , Shih-Wei PENG , Chun-Kuang CHEN , Ru-Gun LIU
IPC: H01L27/02 , H01L21/768 , H01L21/8234 , H01L23/485 , G06F30/394
CPC classification number: H01L27/0207 , H01L21/76895 , H01L21/823418 , H01L21/823437 , H01L21/823475 , H01L21/823425 , H01L21/823431 , H01L23/485 , G06F30/394 , H01L23/528
Abstract: A method is provided, including the following operations: arranging a first gate structure extending continuously above a first active region and a second active region of a substrate; arranging a first separation spacer disposed on the first gate structure to isolate an electronic signal transmitted through a first gate via and a second gate via that are disposed on the first gate structure, wherein the first gate via and the second gate via are arranged above the first active region and the second active region respectively; and arranging a first local interconnect between the first active region and the second active region, wherein the first local interconnect is electrically coupled to a first contact disposed on the first active region and a second contact disposed on the second active region.
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