公开(公告)号：US10985116B2

公开(公告)日：2021-04-20

申请号：US16352838

申请日：2019-03-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Wen Chen ,  Hung-Jui Kuo ,  Ming-Che Ho

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56

Abstract: A semiconductor package and a method of forming the same are disclosed. A method of forming a semiconductor package includes the following operations. A polymer layer is formed over a die. A metal feature is formed in the polymer layer. An argon-containing plasma treatment is performed to the polymer layer and the metal feature.

公开(公告)号：US20200294937A1

公开(公告)日：2020-09-17

申请号：US16352838

申请日：2019-03-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Wen Chen ,  Hung-Jui Kuo ,  Ming-Che Ho

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56

Abstract: A semiconductor package and a method of forming the same are disclosed. A method of forming a semiconductor package includes the following operations. A polymer layer is formed over a die. A metal feature is formed in the polymer layer. An argon-containing plasma treatment is performed to the polymer layer and the metal feature.

公开(公告)号：US09978634B2

公开(公告)日：2018-05-22

申请号：US14632690

申请日：2015-02-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Hsu Yen ,  Bang-Yu Huang ,  Chui-Ya Peng ,  Ching-Wen Chen

IPC: H01L21/762 ,  H01L21/02 ,  H01L29/06 ,  H01L21/3105 ,  C23C16/04 ,  C23C16/505

CPC classification number: H01L21/76224 ,  C23C16/045 ,  C23C16/505 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/31053 ,  H01L21/31056 ,  H01L21/76229 ,  H01L29/0649

Abstract: A method for fabricating a shallow trench isolation includes forming a trench in a substrate, forming a bottom shallow trench isolation dielectric filling a gap of the trench, and forming a top shallow trench isolation dielectric on the bottom shallow trench isolation. The bottom shallow trench isolation dielectric has a concave center portion, and the top shallow trench isolation dielectric is deposited on the bottom shallow trench isolation by a high density plasma chemical vapor deposition process using low deposition to sputter ratio. A semiconductor structure having the shallow trench isolation is also disclosed.