中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

11 records (took 0.016 seconds)

    CELL LAYOUT OF SEMICONDUCTOR DEVICE
    1.
    发明公开
    CELL LAYOUT OF SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20230153508A1

    公开(公告)日：2023-05-18

    申请号：US18156912

    申请日：2023-01-19

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Yi-Lin CHUANG ,  Huang-Yu CHEN ,  Yun-Han LEE

    IPC: G06F30/392 ,  G06F30/394 ,  G06F30/398

    CPC classification number: G06F30/392 ,  G06F30/394 ,  G06F30/398 ,  G06F30/396

    Abstract: A device is disclosed. The cell block includes a pin disposed at a Nth metal layer in a cell layout. The first metal interconnect is disposed at a (N+1)th metal layer above the Nth metal layer and stacked over the pin, and electrically coupled to the pin. The second interconnects are disposed at a (N+2)th metal layer and stacked over the first metal interconnect, and parallel to each other. The second metal interconnects are electrically coupled to the first metal interconnect, and forming an equivalent tapping point of the pin of the cell block. The equivalent tapping point and the pin are vertically overlapped with each other, and fabrication of the device is initiated after a DRC or a SEM simulation test is passed. A first width of at least one first metal interconnect is different from a second width of one of the plurality of second metal interconnects.

    CELL LAYOUT OF SEMICONDUCTOR DEVICE
    2.
    发明申请
    CELL LAYOUT OF SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20210133384A1

    公开(公告)日：2021-05-06

    申请号：US17151189

    申请日：2021-01-17

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Yi-Lin CHUANG ,  Huang-Yu CHEN ,  Yun-Han LEE

    IPC: G06F30/392 ,  G06F30/394 ,  G06F30/398

    Abstract: A device is disclosed. The cell block includes a pin disposed at a Nth metal layer in a cell layout. The first metal interconnect is disposed at a (N+1)th metal layer above the Nth metal layer and stacked over the pin, and electrically coupled to the pin. The second interconnects are disposed at a (N+2)th metal layer and stacked over the first metal interconnect, and parallel to each other. The second metal interconnects are electrically coupled to the first metal interconnect, and forming an equivalent tapping point of the pin of the cell block. The equivalent tapping point and the pin are vertically overlapped with each other, and fabrication of the device is initiated after a DRC or a SEM simulation test is passed. A first via connects the first metal interconnect to the pin, and the at least one first metal interconnect is perpendicular to the pin.

    CELL LAYOUT OF SEMICONDUCTOR DEVICE
    4.
    发明申请
    CELL LAYOUT OF SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20190108302A1

    公开(公告)日：2019-04-11

    申请号：US16210808

    申请日：2018-12-05

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Yi-Lin CHUANG ,  Huang-Yu CHEN ,  Yun-Han LEE

    IPC: G06F17/50

    Abstract: A device is disclosed that includes a cell block, at least one first metal interconnect, and second metal interconnects. The cell block includes a pin disposed at a Nth metal layer in a cell layout. The at least one first metal interconnect is disposed at a (N+1)th metal layer above the Nth metal layer and stacked over the pin, and electrically coupled to the pin. The second interconnects are disposed at a (N+2)th metal layer and stacked over the at least one first metal interconnect, and parallel to each other. The second metal interconnects are electrically coupled to the at least one first metal interconnect, and forming an equivalent tapping point of the pin of the cell block. The equivalent tapping point and the pin are vertically overlapped with each other, and fabrication of the device is initiated after a DRC or a SEM simulation test is passed.

    LAYOUT METHOD AND SYSTEM FOR MULTI-PATTERNING INTEGRATED CIRCUITS
    5.
    发明申请
    LAYOUT METHOD AND SYSTEM FOR MULTI-PATTERNING INTEGRATED CIRCUITS 审中-公开
    多模式集成电路的布局方法和系统

    公开(公告)号：US20140237435A1

    公开(公告)日：2014-08-21

    申请号：US14267013

    申请日：2014-05-01

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Huang-Yu CHEN ,  Tsong-Hua OU ,  Ken-Hsien HSIEH ,  Chin-Hsiung HSU

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G06F17/5072 ,  G06F2217/12

    Abstract: A method identifies, as an independent node, any node representing a circuit pattern in any odd loop of a layout of a region of a layer of an IC that is not included in any other odd loop of the layout. The layer is to have a plurality of circuit patterns to be patterned using at least three photomasks. The method identifies, as a safe independent node, any independent node not closer than a threshold distance from any other independent nodes in another odd loop of the layout. The layout is modified, if the circuit patterns in the layout include any odd loop without any safe independent node, so that that after the modifying, each odd loop has at least one safe independent node.

    Abstract translation: 一种方法将作为独立节点的任何节点表示在不包括在布局的任何其它奇数循环中的IC层的区域的布局的任何奇数循环中的电路图案。 该层将具有使用至少三个光掩模进行图案化的多个电路图案。 该方法将安全独立节点识别为距离布局的另一个奇数循环中任何其他独立节点不超过阈值距离的任何独立节点。 布局被修改，如果布局中的电路图案包括没有任何安全独立节点的任何奇数循环，使得在修改之后，每个奇数循环至少有一个安全独立节点。

    CELL LAYOUT OF SEMICONDUCTOR DEVICE
    6.
    发明申请
    CELL LAYOUT OF SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20170083654A1

    公开(公告)日：2017-03-23

    申请号：US14859162

    申请日：2015-09-18

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Yi-Lin CHUANG ,  Huang-Yu CHEN ,  Yun-Han LEE

    IPC: G06F17/50

    CPC classification number: G06F17/5072 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/62

    Abstract: A cell layout, a cell layout library and a synthesizing method are disclosed. The cell layout includes a cell block and a tapping connector. The cell block has a pin. The pin being disposed at a Nth metal layer in the cell layout. The tapping connector is disposed at a (N+1)th metal layer and a (N+2)th metal layer and stacked above the pin of the cell block. The tapping connector is electrically connected to the pin and forms an equivalent tapping point of the pin of the cell block. N is a positive integer greater than or equal to 1.

    METHOD AND SYSTEM FOR REPLACING A PATTERN IN A LAYOUT
    7.
    发明申请
    METHOD AND SYSTEM FOR REPLACING A PATTERN IN A LAYOUT 有权
    用于在布局中替换图案的方法和系统

    公开(公告)号：US20140059504A1

    公开(公告)日：2014-02-27

    申请号：US14068006

    申请日：2013-10-31

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Huang-Yu CHEN ,  Yuan-Te HOU ,  Chung-Min FU ,  Chung-Hsing WANG ,  Wen-Hao CHEN ,  Yi-Kan CHENG

    IPC: G06F17/50

    CPC classification number: G06F17/5077

    Abstract: A received layout identifies a plurality of circuit components to be included in an integrated circuit (IC) layer for double patterning the layer using two photomasks, the layout including a plurality of first patterns to be included in the first photomask and at least one second pattern to be included in the second photomask. A selected one of the first patterns has first and second endpoints, to be replaced by a replacement pattern connecting the first endpoint to a third endpoint. At least one respective keep-out region is provided adjacent to each respective remaining first pattern except for the selected first pattern. Data are generated representing the replacement pattern, such that no part of the replacement pattern is formed in any of the keep-out regions. Data representing the remaining first patterns and the replacement pattern are output.

    Abstract translation: 接收到的布局标识要包括在集成电路（IC）层中的多个电路组件，用于使用两个光掩模对层进行双重图案化，所述布局包括要包括在第一光掩模中的多个第一图案和至少一个第二图案 被包括在第二个光掩模中。 所选择的第一模式中的一个具有第一和第二端点，被替换为将第一端点连接到第三端点的替换模式。 除了所选择的第一图案之外，至少一个相应的保留区域被设置为与每个相应的剩余第一图案相邻。 生成表示替换图案的数据，使得在任何保留区域中不形成替换图案的一部分。 输出表示剩余的第一图案和替换图案的数据。

    COMPRESSION METHOD AND SYSTEM FOR USE WITH MULTI-PATTERNING
    10.
    发明申请
    COMPRESSION METHOD AND SYSTEM FOR USE WITH MULTI-PATTERNING 审中-公开
    使用多种方式的压缩方法和系统

    公开(公告)号：US20140053118A1

    公开(公告)日：2014-02-20

    申请号：US14064229

    申请日：2013-10-28

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Huang-Yu CHEN ,  Chin-Hsiung HSU ,  Wen-Hao CHEN ,  Chung-Hsing WANG

    IPC: G06F17/50

    CPC classification number: G06F17/50 ,  G03F1/70 ,  G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

    Abstract: A method comprises (a) providing an integrated circuit (IC) layout comprising data representing a plurality of circuit patterns to be formed on or in a single layer of an IC by multi-patterning; (b) dividing the plurality of circuit patterns into two or more groups; (c) assigning the circuit patterns within each group to a respective mask to provide mask assignment data, for forming each group of circuit patterns on or in the single layer of the IC; (d) compressing the mask assignment data; and (e) storing the compressed mask assignment data to a non-transitory machine readable storage medium for use by an electronic design automation tool configured for reconstructing the mask assignment data from the compressed data.

    Abstract translation: 一种方法包括（a）提供集成电路（IC）布局，其包括通过多图案化表示要形成在IC的单层上或其中的多个电路图案的数据; （b）将所述多个电路图案分成两组或更多组; （c）将每个组内的电路图案分配给相应的掩模以提供掩模分配数据，以在IC上或其单层中形成每组电路图案; （d）压缩掩模分配数据; 以及（e）将压缩的掩模分配数据存储到非暂时的机器可读存储介质，以供配置用于从压缩数据重建掩模分配数据的电子设计自动化工具使用。

Patent Agency Ranking