公开(公告)号：US20180315728A1

公开(公告)日：2018-11-01

申请号：US15499962

申请日：2017-04-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hao-Jan PEI ,  Chih-Chiang TSAO ,  Wei-Yu CHEN ,  Hsiu-Jen LIN ,  Ming-Da CHENG ,  Ching-Hua HSIEH ,  Chung-Shi LIU

IPC: H01L23/00 ,  H01L25/10 ,  H01L23/31 ,  H01L23/29 ,  H01L21/56

CPC classification number: H01L24/19 ,  H01L21/565 ,  H01L21/6835 ,  H01L23/293 ,  H01L23/3128 ,  H01L24/13 ,  H01L24/25 ,  H01L24/73 ,  H01L24/96 ,  H01L25/105 ,  H01L2221/68345 ,  H01L2221/68368 ,  H01L2224/13024 ,  H01L2224/19 ,  H01L2224/25171 ,  H01L2224/2518 ,  H01L2224/73209 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/3511

Abstract: Structures and formation methods of a chip package are provided. The method includes forming a protective layer to surround a semiconductor die, and the protective layer has opposing first and second surfaces. The method also includes forming a dielectric layer over the first surface of the protective layer and the semiconductor die. The method further includes forming a conductive feature over the dielectric layer such that the conductive feature is electrically connected to a conductive element of the semiconductor die. In addition, the method includes printing a warpage-control element over the second surface of the protective layer and the semiconductor die such that the semiconductor die is between the warpage-control element and the dielectric layer.

公开(公告)号：US20200279823A1

公开(公告)日：2020-09-03

申请号：US16876371

申请日：2020-05-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hao-Jan PEI ,  Chih-Chiang TSAO ,  Wei-Yu CHEN ,  Hsiu-Jen LIN ,  Ming-Da CHENG ,  Ching-Hua HSIEH ,  Chung-Shi LIU

IPC: H01L23/00 ,  H01L25/10 ,  H01L23/29 ,  H01L21/56 ,  H01L23/31 ,  H01L21/683 ,  H01L25/11

Abstract: A method for forming a package structure is provided. The method includes forming a protective layer to surround a semiconductor die and forming a conductive structure over the protective layer. The method also includes disposing a polymer-containing material over the protective layer to partially surround the conductive structure. The method further includes curing the polymer-containing material to form a warpage-control element.

公开(公告)号：US20190252340A1

公开(公告)日：2019-08-15

申请号：US16398119

申请日：2019-04-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Hao-Jan PEI ,  Chih-Chiang TSAO ,  Wei-Yu CHEN ,  Hsiu-Jen LIN ,  Ming-Da CHENG ,  Ching-Hua HSIEH ,  Chung-Shi LIU

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/683 ,  H01L23/29 ,  H01L21/56 ,  H01L25/11 ,  H01L25/10

CPC classification number: H01L24/19 ,  H01L21/565 ,  H01L21/6835 ,  H01L23/293 ,  H01L23/3128 ,  H01L24/13 ,  H01L24/25 ,  H01L24/73 ,  H01L24/96 ,  H01L25/105 ,  H01L25/115 ,  H01L2221/68345 ,  H01L2221/68368 ,  H01L2224/13024 ,  H01L2224/19 ,  H01L2224/25171 ,  H01L2224/2518 ,  H01L2224/73209 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/3511

Abstract: A package structure is provided. The package structure includes a semiconductor die and a protective layer surrounding the semiconductor die. The package structure also includes a conductive structure and a warpage-control element over a same side of the protective layer. A bottom surface of the warpage-control element is higher than a bottom surface of the conductive structure. The bottom surface of the warpage-control element is lower than a top surface of the conductive bump.