公开(公告)号：US20190385855A1

公开(公告)日：2019-12-19

申请号：US16008321

申请日：2018-06-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jui-Fen CHIEN ,  Chih-Hsiang FAN ,  Hsiao-Kuan WEI ,  Pohan KUNG ,  Hsien-Ming LEE

IPC: H01L21/28 ,  H01L29/49 ,  H01L21/321 ,  H01L29/66

Abstract: Methods of fabricating semiconductor devices are provided. The method includes forming a gate dielectric layer over a substrate. The method also includes depositing a first p-type work function tuning layer over the gate dielectric layer using a first atomic layer deposition (ALD) process with an inorganic precursor. The method further includes forming a second p-type work function tuning layer on the first p-type work function tuning layer using a second atomic layer deposition (ALD) process with an organic precursor. In addition, the method includes forming an n-type work function metal layer over the second p-type work function tuning layer.

公开(公告)号：US20190096680A1

公开(公告)日：2019-03-28

申请号：US15824474

申请日：2017-11-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiao-Kuan WEI ,  Hsien-Ming LEE ,  Chin-You HSU ,  Hsin-Yun HSU ,  Pin-Hsuan YEH

IPC: H01L21/28 ,  H01L29/40 ,  H01L21/285 ,  H01L29/49 ,  H01L21/3213 ,  H01L29/51

Abstract: Generally, the present disclosure provides example embodiments relating to formation of a gate structure of a device, such as in a replacement gate process, and the device formed thereby. In an example method, a gate dielectric layer is formed over an active area on a substrate. A dummy layer that contains a passivating species (such as fluorine) is formed over the gate dielectric layer. A thermal process is performed to drive the passivating species from the dummy layer into the gate dielectric layer. The dummy layer is removed. A metal gate electrode is formed over the gate dielectric layer. The gate dielectric layer includes the passivating species before the metal gate electrode is formed.

公开(公告)号：US20210111027A1

公开(公告)日：2021-04-15

申请号：US17128408

申请日：2020-12-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Yu LIN ,  Chi-Yu CHOU ,  Hsien-Ming LEE ,  Huai-Tei YANG ,  Chun-Chieh WANG ,  Yueh-Ching PAI ,  Chi-Jen YANG ,  Tsung-Ta TANG ,  Yi-Ting WANG

IPC: H01L21/28 ,  H01L29/49 ,  H01L21/3213 ,  H01L21/285

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.