-
公开(公告)号：US09865748B2
公开(公告)日：2018-01-09
申请号：US15488325
申请日：2017-04-14
CPC分类号： H01L29/87 , H01L29/0607 , H01L29/66121
摘要： A semiconductor structure includes a semiconductor substrate having a first electrical portion, a second electrical portion, and a bridged conductive layer. The first electrical portion includes a first semiconductor well, a second semiconductor well in the first semiconductor well, and a third semiconductor well and a fourth semiconductor well in the second semiconductor well. The second electrical portion includes a fifth semiconductor well, a semiconductor layer in the fifth semiconductor well, and a sixth semiconductor well and a seventh semiconductor well in the fifth semiconductor well. The semiconductor layer has separated first and second portions. The bridged conductive layer connects the fourth semiconductor well and the sixth semiconductor well.
-
公开(公告)号：US20220223625A1
公开(公告)日：2022-07-14
申请号：US17323016
申请日：2021-05-18
发明人： Hsin-Chih Chiang , Tung-Yang Lin , Ruey-Hsin Liu , Ming-Ta Lei
IPC分类号： H01L27/12 , H01L23/48 , H01L29/06 , H01L29/10 , H01L29/423 , H01L21/74 , H01L21/762 , H01L21/768 , H01L21/84
摘要： Various embodiments of the present disclosure are directed towards an integrated chip. The integrated chip includes a semiconductor substrate having a device substrate overlying a handle substrate and an insulator layer disposed between the device substrate and the handle substrate. A gate electrode overlies the device substrate between a drain region and a source region. A conductive via extends through the device substrate and the insulator layer to contact the handle substrate. A first isolation structure is disposed within the device substrate and comprises a first isolation segment disposed laterally between the gate electrode and the conductive via. A contact region is disposed within the device substrate between the first isolation segment and the conductive via. A conductive gate electrode directly overlies the first isolation segment and is electrically coupled to the contact region.
-
公开(公告)号：US20160181422A1
公开(公告)日：2016-06-23
申请号：US14580636
申请日：2014-12-23
发明人： Hsin-Chih Chiang , Tung-Yang Lin , Ruey-Hsin Liu , Ming-Ta Lei
CPC分类号： H01L29/7824 , H01L29/0626 , H01L29/063 , H01L29/0634 , H01L29/401 , H01L29/402 , H01L29/66681
摘要： An integrated circuit (IC) includes a high-voltage (HV) MOSFET on a substrate. The substrate includes a handle substrate region, an insulating region, and a silicon region. Source region and drain regions, which have a first conductivity type, are disposed in the silicon region and spaced apart from one another. A gate electrode is disposed over an upper region of the silicon region and is arranged between the source and drain regions. A body region, which has a second conductivity type, is arranged under the gate electrode and separates the source and drain regions. A lateral drain extension region, which has the first conductivity type, is disposed in the upper region of the silicon region and extends laterally between the body and drain regions. A breakdown voltage enhancing region, which has the second conductivity type, is disposed in the silicon region under the lateral drain extension region.
摘要翻译： 集成电路（IC）包括在基板上的高压（HV）MOSFET。 基板包括手柄基板区域，绝缘区域和硅区域。 具有第一导电类型的源极区和漏极区被布置在硅区域中并彼此间隔开。 栅电极设置在硅区域的上部区域上并且布置在源区域和漏极区域之间。 具有第二导电类型的体区被布置在栅电极下方并分离源区和漏区。 具有第一导电类型的横向漏极延伸区域设置在硅区域的上部区域中，并且在主体区域和漏极区域之间横向延伸。 具有第二导电类型的击穿电压增强区域设置在侧向漏极延伸区域下方的硅区域中。
-
公开(公告)号：US11349025B2
公开(公告)日：2022-05-31
申请号：US16227277
申请日：2018-12-20
发明人： Hsin-Chih Chiang
IPC分类号： H01L29/78 , H01L29/10 , H01L29/66 , H01L29/423 , H01L29/08
摘要： In some embodiments, the present disclosure relates to a semiconductor device including a semiconductor region over a bulk oxide, which is over a semiconductor substrate. Above the bulk oxide is a lower source region that is laterally spaced from a lower drain region by a lower portion of the semiconductor region. An upper source region is laterally spaced from an upper drain region by an upper portion of the semiconductor region and is vertically spaced from the lower source region and the lower drain region. The upper source region is coupled to the lower source region, and the upper drain region is coupled to the lower drain region. A gate electrode, coupled to the semiconductor substrate and over a gate oxide, is above the upper portion of the semiconductor region. The lower and upper portions of the semiconductor region respectively include a first channel region and a second channel region.
-
公开(公告)号：US09412863B2
公开(公告)日：2016-08-09
申请号：US14580636
申请日：2014-12-23
发明人： Hsin-Chih Chiang , Tung-Yang Lin , Ruey-Hsin Liu , Ming-Ta Lei
IPC分类号： H01L21/8238 , H01L29/78 , H01L29/66 , H01L29/06 , H01L29/40
CPC分类号： H01L29/7824 , H01L29/0626 , H01L29/063 , H01L29/0634 , H01L29/401 , H01L29/402 , H01L29/66681
摘要： An integrated circuit (IC) includes a high-voltage (HV) MOSFET on a substrate. The substrate includes a handle substrate region, an insulating region, and a silicon region. Source region and drain regions, which have a first conductivity type, are disposed in the silicon region and spaced apart from one another. A gate electrode is disposed over an upper region of the silicon region and is arranged between the source and drain regions. A body region, which has a second conductivity type, is arranged under the gate electrode and separates the source and drain regions. A lateral drain extension region, which has the first conductivity type, is disposed in the upper region of the silicon region and extends laterally between the body and drain regions. A breakdown voltage enhancing region, which has the second conductivity type, is disposed in the silicon region under the lateral drain extension region.
摘要翻译： 集成电路（IC）包括在基板上的高压（HV）MOSFET。 基板包括手柄基板区域，绝缘区域和硅区域。 具有第一导电类型的源极区和漏极区被布置在硅区域中并彼此间隔开。 栅电极设置在硅区域的上部区域上并且布置在源区域和漏极区域之间。 具有第二导电类型的体区被布置在栅电极下方并分离源区和漏区。 具有第一导电类型的横向漏极延伸区域设置在硅区域的上部区域中，并且在主体区域和漏极区域之间横向延伸。 具有第二导电类型的击穿电压增强区域设置在侧向漏极延伸区域下方的硅区域中。
-
公开(公告)号：US11508757B2
公开(公告)日：2022-11-22
申请号：US17323016
申请日：2021-05-18
发明人： Hsin-Chih Chiang , Tung-Yang Lin , Ruey-Hsin Liu , Ming-Ta Lei
IPC分类号： H01L27/12 , H01L23/48 , H01L29/06 , H01L29/10 , H01L21/84 , H01L29/423 , H01L21/74 , H01L21/762 , H01L21/768
摘要： Various embodiments of the present disclosure are directed towards an integrated chip. The integrated chip includes a semiconductor substrate having a device substrate overlying a handle substrate and an insulator layer disposed between the device substrate and the handle substrate. A gate electrode overlies the device substrate between a drain region and a source region. A conductive via extends through the device substrate and the insulator layer to contact the handle substrate. A first isolation structure is disposed within the device substrate and comprises a first isolation segment disposed laterally between the gate electrode and the conductive via. A contact region is disposed within the device substrate between the first isolation segment and the conductive via. A conductive gate electrode directly overlies the first isolation segment and is electrically coupled to the contact region.
-
公开(公告)号：US09627551B2
公开(公告)日：2017-04-18
申请号：US14026580
申请日：2013-09-13
CPC分类号： H01L29/87 , H01L29/0607 , H01L29/66121
摘要： The disclosure provides an ultrahigh-voltage (UHV) semiconductor structure including a first electrical portion, a second electrical portion and a bridged conductive layer. In which, the first electrical portion and the second electrical portion are isolated, and directly connected to each other through the bridged conductive layer. Thus, there is no current leakage occurring in the UHV semiconductor structure disclosed in this disclosure. And a method for manufacturing the UHV semiconductor structure also provides herein.
-
-
-
-
-
-
搜索结果
7 条记录 (耗时 0.015 秒)