公开(公告)号：US20210273119A1

公开(公告)日：2021-09-02

申请号：US17324402

申请日：2021-05-19

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Liang-Yu Su ,  Chih-Wen Yao ,  Hsiao-Chin Tuan ,  Ming-Ta Lei

IPC分类号： H01L29/93 ,  H01L27/08 ,  H01L29/66 ,  H01L29/06

摘要： Various embodiments of the present disclosure are directed towards a method for forming a varactor comprising a reduced surface field (RESURF) region. The method includes forming a drift region having a first doping type within a substrate. A RESURF region having a second doping type is formed within the substrate such that the RESURF region is below the drift region. A gate structure is formed on the substrate. A pair of contact regions is formed within the substrate on opposing sides of the gate structure. The contact regions respectively abut the drift region and have the first doping type, and wherein the first doping type is opposite the second doping type.

公开(公告)号：US11107899B2

公开(公告)日：2021-08-31

申请号：US16837401

申请日：2020-04-01

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Chang Cheng ,  Fu-Yu Chu ,  Ming-Ta Lei ,  Ruey-Hsin Liu ,  Shih-Fen Huang

IPC分类号： H01L29/78 ,  H01L29/423 ,  H01L21/265 ,  H01L21/28 ,  H01L29/06 ,  H01L29/08 ,  H01L29/49

摘要： A semiconductor device and method for forming the semiconductor device are provided. In some embodiments, a semiconductor substrate comprises a device region. An isolation structure extends laterally in a closed path to demarcate the device region. A first source/drain region and a second source/drain region are in the device region and laterally spaced. A sidewall of the first source/drain region directly contacts the isolation structure at a first isolation structure sidewall, and remaining sidewalls of the first source/drain region are spaced from the isolation structure. A selectively-conductive channel is in the device region, and extends laterally from the first source/drain region to the second source/drain region. A plate comprises a central portion and a first peripheral portion. The central portion overlies the selectively-conductive channel, and the first peripheral portion protrudes from the central portion towards the first isolation structure sidewall.

公开(公告)号：US10680019B2

公开(公告)日：2020-06-09

申请号：US16382455

申请日：2019-04-12

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chen-Liang Chu ,  Chih-Wen Albert Yao ,  Ruey-Hsin Liu ,  Ming-Ta Lei

IPC分类号： H01L27/12 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L21/28

摘要： Some embodiments of the present disclosure relate to a method of forming a transistor. The method includes forming a gate dielectric over a substrate and forming a gate over the gate dielectric. The gate includes polysilicon extending between a first outermost sidewall and a second outermost sidewall of the gate. A mask is formed over the gate. The mask exposes a first gate region extending to the first outermost sidewall and covers a second gate region extending between the first gate region and the second outermost sidewall. Dopants are selectively implanted into the first gate region according to the mask. Source and drain regions are formed within the substrate. The source region and the drain region are asymmetric with respect to an interface of the first gate region and the second gate region and extend to substantially equal distances past the first and second outermost sidewalls of the gate, respectively.

公开(公告)号：US09412863B2

公开(公告)日：2016-08-09

申请号：US14580636

申请日：2014-12-23

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsin-Chih Chiang ,  Tung-Yang Lin ,  Ruey-Hsin Liu ,  Ming-Ta Lei

IPC分类号： H01L21/8238 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/40

CPC分类号： H01L29/7824 ,  H01L29/0626 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/401 ,  H01L29/402 ,  H01L29/66681

摘要： An integrated circuit (IC) includes a high-voltage (HV) MOSFET on a substrate. The substrate includes a handle substrate region, an insulating region, and a silicon region. Source region and drain regions, which have a first conductivity type, are disposed in the silicon region and spaced apart from one another. A gate electrode is disposed over an upper region of the silicon region and is arranged between the source and drain regions. A body region, which has a second conductivity type, is arranged under the gate electrode and separates the source and drain regions. A lateral drain extension region, which has the first conductivity type, is disposed in the upper region of the silicon region and extends laterally between the body and drain regions. A breakdown voltage enhancing region, which has the second conductivity type, is disposed in the silicon region under the lateral drain extension region.

摘要翻译： 集成电路（IC）包括在基板上的高压（HV）MOSFET。 基板包括手柄基板区域，绝缘区域和硅区域。 具有第一导电类型的源极区和漏极区被布置在硅区域中并彼此间隔开。 栅电极设置在硅区域的上部区域上并且布置在源区域和漏极区域之间。 具有第二导电类型的体区被布置在栅电极下方并分离源区和漏区。 具有第一导电类型的横向漏极延伸区域设置在硅区域的上部区域中，并且在主体区域和漏极区域之间横向延伸。 具有第二导电类型的击穿电压增强区域设置在侧向漏极延伸区域下方的硅区域中。

公开(公告)号：US20220223625A1

公开(公告)日：2022-07-14

申请号：US17323016

申请日：2021-05-18

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsin-Chih Chiang ,  Tung-Yang Lin ,  Ruey-Hsin Liu ,  Ming-Ta Lei

IPC分类号： H01L27/12 ,  H01L23/48 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/84

摘要： Various embodiments of the present disclosure are directed towards an integrated chip. The integrated chip includes a semiconductor substrate having a device substrate overlying a handle substrate and an insulator layer disposed between the device substrate and the handle substrate. A gate electrode overlies the device substrate between a drain region and a source region. A conductive via extends through the device substrate and the insulator layer to contact the handle substrate. A first isolation structure is disposed within the device substrate and comprises a first isolation segment disposed laterally between the gate electrode and the conductive via. A contact region is disposed within the device substrate between the first isolation segment and the conductive via. A conductive gate electrode directly overlies the first isolation segment and is electrically coupled to the contact region.

公开(公告)号：US20200227528A1

公开(公告)日：2020-07-16

申请号：US16837401

申请日：2020-04-01

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Chang Cheng ,  Fu-Yu Chu ,  Ming-Ta Lei ,  Ruey-Hsin Liu ,  Shih-Fen Huang

IPC分类号： H01L29/423 ,  H01L29/78 ,  H01L21/265 ,  H01L21/28 ,  H01L29/06 ,  H01L29/08

摘要： A semiconductor device and method for forming the semiconductor device are provided. In some embodiments, a semiconductor substrate comprises a device region. An isolation structure extends laterally in a closed path to demarcate the device region. A first source/drain region and a second source/drain region are in the device region and laterally spaced. A sidewall of the first source/drain region directly contacts the isolation structure at a first isolation structure sidewall, and remaining sidewalls of the first source/drain region are spaced from the isolation structure. A selectively-conductive channel is in the device region, and extends laterally from the first source/drain region to the second source/drain region. A plate comprises a central portion and a first peripheral portion. The central portion overlies the selectively-conductive channel, and the first peripheral portion protrudes from the central portion towards the first isolation structure sidewall.

公开(公告)号：US10164037B2

公开(公告)日：2018-12-25

申请号：US15475294

申请日：2017-03-31

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ker-Hsiao Huo ,  Kong-Beng Thei ,  Chih-Wen Albert Yao ,  Fu-Jier Fan ,  Chen-Liang Chu ,  Ta-Yuan Kung ,  Yi-Huan Chen ,  Yu-Bin Zhao ,  Ming-Ta Lei ,  Li-Hsuan Yeh

IPC分类号： H01L29/423 ,  H01L21/28 ,  H01L29/40 ,  H01L29/06 ,  H01L29/08

摘要： A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate having a top surface, a source region, and a drain region. The semiconductor device structure includes a gate structure over the top surface and extending into the semiconductor substrate. The gate structure in the semiconductor substrate is between the source region and the drain region and separates the source region from the drain region. The semiconductor device structure includes an isolation structure in the semiconductor substrate and surrounding the source region, the drain region, and the gate structure in the semiconductor substrate.

公开(公告)号：US11508757B2

公开(公告)日：2022-11-22

申请号：US17323016

申请日：2021-05-18

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsin-Chih Chiang ,  Tung-Yang Lin ,  Ruey-Hsin Liu ,  Ming-Ta Lei

IPC分类号： H01L27/12 ,  H01L23/48 ,  H01L29/06 ,  H01L29/10 ,  H01L21/84 ,  H01L29/423 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768

摘要： Various embodiments of the present disclosure are directed towards an integrated chip. The integrated chip includes a semiconductor substrate having a device substrate overlying a handle substrate and an insulator layer disposed between the device substrate and the handle substrate. A gate electrode overlies the device substrate between a drain region and a source region. A conductive via extends through the device substrate and the insulator layer to contact the handle substrate. A first isolation structure is disposed within the device substrate and comprises a first isolation segment disposed laterally between the gate electrode and the conductive via. A contact region is disposed within the device substrate between the first isolation segment and the conductive via. A conductive gate electrode directly overlies the first isolation segment and is electrically coupled to the contact region.

公开(公告)号：US11444169B2

公开(公告)日：2022-09-13

申请号：US16929640

申请日：2020-07-15

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chen-Liang Chu ,  Chien-Chih Chou ,  Chih-Chang Cheng ,  Yi-Huan Chen ,  Kong-Beng Thei ,  Ming-Ta Lei ,  Ruey-Hsin Liu ,  Ta-Yuan Kung

IPC分类号： H01L29/423 ,  H01L29/06 ,  H01L29/08 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L29/45 ,  H01L21/28 ,  H01L21/285 ,  H01L21/762

摘要： A transistor device with a recessed gate structure is provided. In some embodiments, the transistor device comprises a semiconductor substrate comprising a device region surrounded by an isolation structure and a pair of source/drain regions disposed in the device region and laterally spaced apart one from another in a first direction. A gate structure overlies the device region and the isolation structure and arranged between the pair of source/drain regions. The gate structure comprises a pair of recess regions disposed on opposite sides of the device region in a second direction perpendicular to the first direction. A channel region is disposed in the device region underneath the gate structure. The channel region has a channel width extending in the second direction from one of the recess regions to the other one of the recess regions.

公开(公告)号：US20210134964A1

公开(公告)日：2021-05-06

申请号：US16671336

申请日：2019-11-01

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chia-Cheng Ho ,  Ming-Ta Lei ,  Yu-Chang Jong

IPC分类号： H01L29/40 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L23/522 ,  H01L23/528

摘要： Various embodiments of the present disclosure are directed towards an integrated chip including a field plate. A gate electrode overlies a substrate between a source region and a drain region. A drift region is arranged laterally between the gate electrode and the drain region. A plurality of inter-level dielectric (ILD) layers overlie the substrate. The plurality of ILD layers includes a first ILD layer underlying a second ILD layer. A plurality of conductive interconnect layers is disposed within the plurality of ILD layers. The field plate extends from a top surface of the first ILD layer to a point that is vertically separated from the drift region by the first ILD layer. The field plate is laterally offset the gate electrode by a non-zero distance in a direction toward the drain region. The field plate includes a same material as at least one of the plurality of conductive interconnect layers.