公开(公告)号：US20220367684A1

公开(公告)日：2022-11-17

申请号：US17815913

申请日：2022-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Xusheng WU ,  Chang-Miao LIU ,  Huiling SHANG

IPC: H01L29/66 ,  H01L29/786 ,  H01L29/08 ,  H01L29/423 ,  H01L21/762

Abstract: A method includes forming a semiconductor substrate having an oxide layer embedded therein, forming a multi-layer (ML) stack including alternating channel layers and non-channel layers over the semiconductor substrate, forming a dummy gate stack over the ML, forming an S/D recess in the ML to expose the oxide layer, forming an epitaxial S/D feature in the S/D recess, removing the non-channel layers from the ML to form openings between the channel layers, where the openings are formed adjacent to the epitaxial S/D feature, and forming a high-k metal gate stack (HKMG) in the openings between the channel layers and in place of the dummy gate stack.

公开(公告)号：US20200343362A1

公开(公告)日：2020-10-29

申请号：US16392130

申请日：2019-04-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Xusheng WU ,  Chang-Miao LIU ,  Huiling SHANG

IPC: H01L29/66 ,  H01L29/423 ,  H01L21/8234 ,  H01L29/78 ,  H01L27/088 ,  H01L29/49 ,  H01L21/28

Abstract: A structure and a formation method of a semiconductor device are provided. The method includes forming a dummy gate stack over a semiconductor substrate. The dummy gate stack has a dummy gate electrode and a dummy gate dielectric layer. The method also includes forming spacer elements over sidewalls of the dummy gate stack and partially removing the dummy gate electrode to form a recess. The method further includes partially removing the spacer elements to enlarge the recess and removing a remaining portion of the dummy gate electrode to expose the dummy gate dielectric layer. In addition, the method includes doping the spacer elements after the remaining portion of the dummy gate electrode is removed and removing the dummy gate dielectric layer. The method further includes forming a metal gate stack in the recess.

公开(公告)号：US20240250152A1

公开(公告)日：2024-07-25

申请号：US18623390

申请日：2024-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Xusheng Wu ,  Chang-Miao Liu ,  Huiling SHANG

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/225 ,  H01L21/265 ,  H01L21/762 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/66742 ,  H01L21/7624 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66787 ,  H01L29/78603 ,  H01L29/78696 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/2253 ,  H01L21/26533 ,  H01L29/0673

Abstract: A semiconductor structure includes a substrate, an oxide layer disposed over the substrate, a stack of semiconductor layers disposed over the oxide layer, and an epitaxial source/drain (S/D) feature disposed adjacent to the stack of semiconductor layers. A portion of the epitaxial S/D feature is horizontally surrounded by the oxide layer.

公开(公告)号：US20240096971A1

公开(公告)日：2024-03-21

申请号：US18521701

申请日：2023-11-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Xusheng WU ,  Chang-Miao LIU ,  Ying-Keung LEUNG ,  Huiling SHANG ,  Youbo LIN

IPC: H01L29/40 ,  H01L21/283 ,  H01L21/285 ,  H01L21/768 ,  H01L29/45 ,  H01L29/66

CPC classification number: H01L29/401 ,  H01L21/283 ,  H01L21/28518 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76877 ,  H01L29/456 ,  H01L29/665

Abstract: A method including providing a device including a gate structure and a source/drain feature adjacent to the gate structure. An insulating layer (e.g., CESL, ILD) is formed over the source/drain feature. A trench is etched in the insulating layer to expose a surface of the source/drain feature. A semiconductor material is then formed in the etched trench on the surface of the source/drain feature. The semiconductor material is converted to a silicide.

公开(公告)号：US20210226018A1

公开(公告)日：2021-07-22

申请号：US16746618

申请日：2020-01-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Xusheng WU ,  Chang-Miao LUI ,  Ying-Keung LEUNG ,  Huiling SHANG ,  Youbo LIN

IPC: H01L29/40 ,  H01L21/768 ,  H01L29/45 ,  H01L21/283

Abstract: A method including providing a device including a gate structure and a source/drain feature adjacent to the gate structure. An insulating layer (e.g., CESL, ILD) is formed over the source/drain feature. A trench is etched in the insulating layer to expose a surface of the source/drain feature. A semiconductor material is then formed in the etched trench on the surface of the source/drain feature. The semiconductor material is converted to a silicide.

公开(公告)号：US20220367685A1

公开(公告)日：2022-11-17

申请号：US17876448

申请日：2022-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Xusheng WU ,  Chang-Miao LIU ,  Huiling SHANG

IPC: H01L29/66 ,  H01L29/786 ,  H01L29/08 ,  H01L29/423 ,  H01L21/762

Abstract: A method includes forming a semiconductor substrate having an oxide layer embedded therein, forming a multi-layer (ML) stack including alternating channel layers and non-channel layers over the semiconductor substrate, forming a dummy gate stack over the ML, forming an S/D recess in the ML to expose the oxide layer, forming an epitaxial S/D feature in the S/D recess, removing the non-channel layers from the ML to form openings between the channel layers, where the openings are formed adjacent to the epitaxial S/D feature, and forming a high-k metal gate stack (HKMG) in the openings between the channel layers and in place of the dummy gate stack.

公开(公告)号：US20220238661A1

公开(公告)日：2022-07-28

申请号：US17658779

申请日：2022-04-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Xusheng WU ,  Chang-Miao LIU ,  Ying-Keung LEUNG ,  Huiling SHANG ,  Youbo LIN

IPC: H01L29/40 ,  H01L21/768 ,  H01L21/283 ,  H01L29/45 ,  H01L21/285 ,  H01L29/66

Abstract: A method including providing a device including a gate structure and a source/drain feature adjacent to the gate structure. An insulating layer (e.g., CESL, ILD) is formed over the source/drain feature. A trench is etched in the insulating layer to expose a surface of the source/drain feature. A semiconductor material is then formed in the etched trench on the surface of the source/drain feature. The semiconductor material is converted to a silicide.