公开(公告)号：US20180152193A1

公开(公告)日：2018-05-31

申请号：US15711201

申请日：2017-09-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sandeep Kumar GOEL ,  Ji-Jan CHEN ,  Stanley JOHN ,  Yun-Han LEE ,  Yen-Hao HUANG

IPC: H03L7/23 ,  H03L7/095 ,  H03L7/091

CPC classification number: H03L7/23 ,  H03K19/21 ,  H03L7/091 ,  H03L7/095

Abstract: A clock distribution circuit configured to output a clock signal includes a first circuit configured to use a reference clock signal to provide first and second reference signals, wherein the second reference signal indicates whether the first reference signal is locked with the reference clock signal; a second circuit configured to use the reference clock signal to provide an output signal and an indication signal indicative whether the output signal is locked with the reference clock signal; and a monitor circuit, coupled to the first and second circuits, and configured to use at least one of the first reference signal, the second reference signal, the output signal, and the indication signal to determine whether the second circuit is functioning correctly.

公开(公告)号：US20210281268A1

公开(公告)日：2021-09-09

申请号：US17330818

申请日：2021-05-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sandeep Kumar GOEL ,  Ji-Jan CHEN ,  Stanley JOHN ,  Yun-Han LEE ,  Yen-Hao HUANG

IPC: H03L7/23 ,  H03L7/091 ,  H03L7/095

Abstract: A clock distribution circuit configured to output a clock signal includes a first circuit configured to use a reference clock signal to provide first and second reference signals, wherein the second reference signal indicates whether the first reference signal is locked with the reference clock signal; a second circuit configured to use the reference clock signal to provide an output signal and an indication signal indicative whether the output signal is locked with the reference clock signal; and a monitor circuit, coupled to the first and second circuits, and configured to use at least one of the first reference signal, the second reference signal, the output signal, and the indication signal to determine whether the second circuit is functioning correctly.

公开(公告)号：US20200304133A1

公开(公告)日：2020-09-24

申请号：US16894607

申请日：2020-06-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sandeep Kumar GOEL ,  Ji-Jan CHEN ,  Stanley JOHN ,  Yun-Han LEE ,  Yen-Hao HUANG

IPC: H03L7/23 ,  H03L7/091 ,  H03L7/095

Abstract: A clock distribution circuit configured to output a clock signal includes a first circuit configured to use a reference clock signal to provide first and second reference signals, wherein the second reference signal indicates whether the first reference signal is locked with the reference clock signal; a second circuit configured to use the reference clock signal to provide an output signal and an indication signal indicative whether the output signal is locked with the reference clock signal; and a monitor circuit, coupled to the first and second circuits, and configured to use at least one of the first reference signal, the second reference signal, the output signal, and the indication signal to determine whether the second circuit is functioning correctly.

公开(公告)号：US20180164369A1

公开(公告)日：2018-06-14

申请号：US15602365

申请日：2017-05-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Sandeep Kumar GOEL ,  Stanley JOHN ,  Ji-Jan CHEN ,  Yun-Han LEE

IPC: G01R31/3183 ,  H03K19/20 ,  G01R31/28

CPC classification number: G01R31/3183 ,  G01R31/2834 ,  H03K19/20

Abstract: A device includes a fault generation circuit and a first fault injection circuit. The fault generation circuit is configured to generate a fault signal and a plurality of control signals according to a mode signal. The first fault injection circuit is configured to inject a first final fault signal to an under-test device based on the fault signal and the plurality of control signals, in order to verify robustness of the under-test device.