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公开(公告)号：US20230113905A1
公开(公告)日：2023-04-13
申请号：US18080680
申请日：2022-12-13
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Sandeep Kumar GOEL , Yun-Han LEE , Saman M.I. ADHAM , Marat GERSHOIG
IPC: G01R31/3177 , G01R31/3185 , G01R31/28 , G01R31/317
Abstract: In one embodiment, a device comprises: a first die having disposed thereon a first plurality of latches wherein ones of the first plurality of latches are operatively connected to an adjacent one of the first plurality of latches; and a second die having disposed thereon a second plurality of latches wherein ones of the second plurality of latches are operatively connected to an adjacent one of the second plurality of latches. Each latch of the first plurality of latches on said first die corresponds to a latch in the second plurality of latches on said second die. Each set of corresponding latches are operatively connected. A scan path comprises a closed loop comprising each of said first and second plurality of latches. One of the second plurality of latches is operatively connected to another one of the second plurality of latches via an inverter.
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公开(公告)号：US20200272777A1
公开(公告)日：2020-08-27
申请号：US16871841
申请日：2020-05-11
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yi-Lin CHUANG , Ching-Fang CHEN , Wei-Li CHEN , Wei-Pin CHANGCHIEN , Yung-Chin HOU , Yun-Han LEE
IPC: G06F30/27 , G06N20/00 , G06F30/30 , G06F30/3308 , G06F30/337 , G06F30/373
Abstract: Electronic design automation (EDA) of the present disclosure, in various embodiments, optimizes designing, simulating, analyzing, and verifying of one or more electronic architectural designs for an electronic device. The EDA of the present disclosure identifies one or more electronic architectural features from the one or more electronic architectural designs. In some situations, the EDA of the present disclosure can manipulate one or more electronic architectural models over multiple iterations using a machine learning process until one or more electronic architectural models from among the one or more electronic architectural models satisfy one or more electronic design targets. The EDA of the present disclosure substitutes the one or more electronic architectural models that satisfy the one or more electronic design targets for the one or more electronic architectural features in the one or more electronic architectural designs to optimize the one or more electronic architectural designs. The EDA of the present disclosure can substitute the one or more electronic architectural models before, during, and/or after designing, simulating, analyzing, and/or verifying of the one or more electronic architectural designs to effectively decrease the time to market (TTM) for the electronic device.
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公开(公告)号：US20170161420A1
公开(公告)日：2017-06-08
申请号：US14963151
申请日：2015-12-08
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Yung-Chin HOU , Sandeep Kumar GOEL , Yun-Han LEE
IPC: G06F17/50 , H01L21/768 , H01L23/528 , H01L25/065 , H01L21/48 , H01L23/522 , H01L23/498 , H01L25/00
CPC classification number: G06F17/5072 , G06F17/5077 , H01L21/486 , H01L21/76883 , H01L21/76898 , H01L23/147 , H01L23/481 , H01L23/49827 , H01L23/49838 , H01L23/522 , H01L23/5226 , H01L23/528 , H01L25/0657 , H01L25/50 , H01L2225/06541 , H01L2225/06548
Abstract: A partition method includes sorting the plurality of components into a plurality of partitions according to a set of partition criteria and sorting the plurality of components of each partition into a first stack and a second stack according to a set of stack criteria, and the first stack includes a plurality of higher pitch metal layers and the second stack includes a plurality of lower pitch metal layers. The partition criteria include size, power and speed of the component, and the stack criteria include a pitch of a metal layer.
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公开(公告)号：US20170083654A1
公开(公告)日：2017-03-23
申请号：US14859162
申请日：2015-09-18
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Yi-Lin CHUANG , Huang-Yu CHEN , Yun-Han LEE
IPC: G06F17/50
CPC classification number: G06F17/5072 , G06F17/5077 , G06F17/5081 , G06F2217/62
Abstract: A cell layout, a cell layout library and a synthesizing method are disclosed. The cell layout includes a cell block and a tapping connector. The cell block has a pin. The pin being disposed at a Nth metal layer in the cell layout. The tapping connector is disposed at a (N+1)th metal layer and a (N+2)th metal layer and stacked above the pin of the cell block. The tapping connector is electrically connected to the pin and forms an equivalent tapping point of the pin of the cell block. N is a positive integer greater than or equal to 1.
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公开(公告)号：US20210281268A1
公开(公告)日：2021-09-09
申请号：US17330818
申请日：2021-05-26
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Sandeep Kumar GOEL , Ji-Jan CHEN , Stanley JOHN , Yun-Han LEE , Yen-Hao HUANG
Abstract: A clock distribution circuit configured to output a clock signal includes a first circuit configured to use a reference clock signal to provide first and second reference signals, wherein the second reference signal indicates whether the first reference signal is locked with the reference clock signal; a second circuit configured to use the reference clock signal to provide an output signal and an indication signal indicative whether the output signal is locked with the reference clock signal; and a monitor circuit, coupled to the first and second circuits, and configured to use at least one of the first reference signal, the second reference signal, the output signal, and the indication signal to determine whether the second circuit is functioning correctly.
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Patent Agency Ranking
公开(公告)号：US20210133384A1
公开(公告)日：2021-05-06
申请号：US17151189
申请日：2021-01-17
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Yi-Lin CHUANG , Huang-Yu CHEN , Yun-Han LEE
IPC: G06F30/392 , G06F30/394 , G06F30/398
Abstract: A device is disclosed. The cell block includes a pin disposed at a Nth metal layer in a cell layout. The first metal interconnect is disposed at a (N+1)th metal layer above the Nth metal layer and stacked over the pin, and electrically coupled to the pin. The second interconnects are disposed at a (N+2)th metal layer and stacked over the first metal interconnect, and parallel to each other. The second metal interconnects are electrically coupled to the first metal interconnect, and forming an equivalent tapping point of the pin of the cell block. The equivalent tapping point and the pin are vertically overlapped with each other, and fabrication of the device is initiated after a DRC or a SEM simulation test is passed. A first via connects the first metal interconnect to the pin, and the at least one first metal interconnect is perpendicular to the pin.
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公开(公告)号：US20200304133A1
公开(公告)日：2020-09-24
申请号：US16894607
申请日：2020-06-05
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Sandeep Kumar GOEL , Ji-Jan CHEN , Stanley JOHN , Yun-Han LEE , Yen-Hao HUANG
Abstract: A clock distribution circuit configured to output a clock signal includes a first circuit configured to use a reference clock signal to provide first and second reference signals, wherein the second reference signal indicates whether the first reference signal is locked with the reference clock signal; a second circuit configured to use the reference clock signal to provide an output signal and an indication signal indicative whether the output signal is locked with the reference clock signal; and a monitor circuit, coupled to the first and second circuits, and configured to use at least one of the first reference signal, the second reference signal, the output signal, and the indication signal to determine whether the second circuit is functioning correctly.
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公开(公告)号：US20190332161A1
公开(公告)日：2019-10-31
申请号：US16505347
申请日：2019-07-08
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Kai-Yuan TING , Shereef SHEHATA , Tze-Chiang HUANG , Sandeep Kumar GOEL , Mei WONG , Yun-Han LEE
IPC: G06F1/3228 , G06F1/28
Abstract: A device for power estimation is disclosed. The device includes a transformer circuit coupled with a processing circuit and a transaction interface. The transformer circuit is configured to count performance activities executed in the processing circuit and to compare count values of the performance activities with a pre-determined value to determine a power state of the processing circuit. The transaction interface is configured to receive a request from the processing circuit and record a first timestamp, and further configured to receive a response from a memory model and record a second timestamp, the transaction interface being further configured to record a time difference between the first timestamp and the second timestamp as a time difference. The transformer circuit is further configured to determine the power state of the processing circuit based on both of the count values and the time difference.
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公开(公告)号：US20180268096A1
公开(公告)日：2018-09-20
申请号：US15724663
申请日：2017-10-04
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yi-Lin CHUANG , Ching-Fang CHEN , Wei-Li CHEN , Wei-Pin CHANGCHIEN , Yung-Chin HOU , Yun-Han LEE
Abstract: Electronic design automation (EDA) of the present disclosure, in various embodiments, optimizes designing, simulating, analyzing, and verifying of one or more electronic architectural designs for an electronic device. The EDA of the present disclosure identifies one or more electronic architectural features from the one or more electronic architectural designs. In some situations, the EDA of the present disclosure can manipulate one or more electronic architectural models over multiple iterations using a machine learning process until one or more electronic architectural models from among the one or more electronic architectural models satisfy one or more electronic design targets. The EDA of the present disclosure substitutes the one or more electronic architectural models that satisfy the one or more electronic design targets for the one or more electronic architectural features in the one or more electronic architectural designs to optimize the one or more electronic architectural designs. The EDA of the present disclosure can substitute the one or more electronic architectural models before, during, and/or after designing, simulating, analyzing, and/or verifying of the one or more electronic architectural designs to effectively decrease the time to market (TTM) for the electronic device.
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公开(公告)号：US20170076029A1
公开(公告)日：2017-03-16
申请号：US15260143
申请日：2016-09-08
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Tze-Chiang HUANG , Kai-Yuan TING , Sandeep Kumar GOEL , Yun-Han LEE , Shereef SHEHATA , Mei WONG
Abstract: A method is disclosed that includes providing an IP bank, an application bank, and a technology bank; generating a hierarchical table based on the IP bank and the application bank; performing an estimation of at least one of a performance value, a power value, an area value and a cost value, which corresponds to the hierarchical table, by using the technology bank, to output an result data as a basis of fabrication of a system.
Abstract translation: 公开了一种包括提供IP银行，应用银行和技术银行的方法; 基于IP银行和应用银行生成分层表; 通过使用技术组对与分层表相对应的性能值，功率值，面积值和成本值中的至少一个进行估计，输出作为系统的制造基础的结果数据 。
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