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1.发明授权MIM/RRAM structure with improved capacitance and reduced leakage current 有权MIM / RRAM结构具有改进的电容和减小的漏电流公开(公告)号：US09543375B2
公开(公告)日：2017-01-10
申请号：US14316910
申请日：2014-06-27
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Jian-Shiou Huang , Yao-Wen Chang , Hsing-Lien Lin , Cheng-Yuan Tsai , Chia-Shiung Tsai
CPC classification number: H01L28/40 , H01L21/02112 , H01L21/0214 , H01L21/02164 , H01L21/0217 , H01L21/02178 , H01L21/02181 , H01L21/02266 , H01L23/5223 , H01L29/88 , H01L45/08 , H01L45/10
Abstract: Some embodiments of the present disclosure provide an integrated circuit (IC) device including a metal-insulator-metal (MIM) capacitor structure. The MIM capacitor structure includes a lower metal capacitor electrode, an upper metal capacitor electrode, and a capacitor dielectric separating the lower metal capacitor electrode from the upper metal capacitor electrode. The capacitor dielectric is made up of an amorphous oxide/nitride matrix and a plurality of metal or metal oxide/nitride nano-particles that are randomly distributed over the volume of amorphous oxide/nitride matrix.
Abstract translation: 本公开的一些实施例提供了包括金属 - 绝缘体 - 金属（MIM）电容器结构的集成电路（IC）装置。 MIM电容器结构包括下金属电容器电极，上金属电容器电极和将下金属电容器电极与上金属电容器电极分离的电容器电介质。 电容器电介质由无定形氧化物/氮化物基体和随机分布在无定形氧化物/氮化物基体的体积上的多个金属或金属氧化物/氮化物纳米颗粒构成。
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公开(公告)号：US09502649B2
公开(公告)日：2016-11-22
申请号：US14645932
申请日：2015-03-12
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Jian-Shiou Huang , Cheng-Yuan Tsai , Yao-Wen Chang
IPC: H01L45/00
CPC classification number: H01L45/16 , H01L45/08 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/1675
Abstract: An integrated circuit with a multilayer bottom electrode, and a corresponding method for manufacturing the integrated circuit, are provided. An insulating layer includes an opening, and a bottom electrode substantially fills the opening. The bottom electrode includes a plurality of layers laterally or vertically stacked upon each other, and lining the opening. The layers of the plurality include corresponding surfaces facing an interior of the opening and extending respectively at angles relative to a top surface of the bottom electrode. Further, the layers of the plurality include corresponding regions of increased resistance or height extending along the corresponding surfaces. A dielectric layer is arranged over the insulating layer and the bottom electrode, and a top electrode arranged over the dielectric layer.
Abstract translation: 提供了具有多层底电极的集成电路及其制造方法。 绝缘层包括开口，底部电极基本上填充开口。 底部电极包括彼此横向或垂直堆叠的多个层，并且衬里该开口。 多个层包括相对于开口内部的对应表面，并分别以相对于底部电极的顶表面的角度延伸。 此外，多个层包括相应的沿着相应表面延伸的电阻或高度的对应区域。 电介质层设置在绝缘层和底电极之上，以及布置在电介质层上的顶电极。
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公开(公告)号：US09257642B1
公开(公告)日：2016-02-09
申请号：US14332577
申请日：2014-07-16
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yao-Wen Chang , Jian-Shiou Huang , Hsing-Lien Lin , Cheng-Yuan Tsai , Chia-Shiung Tsai
IPC: H01L27/24 , H01L27/112 , H01L29/417 , H01L29/45 , H01L29/86 , H01L45/00
CPC classification number: H01L45/1253 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/16
Abstract: Some embodiments relate to a resistive random access memory (RRAM). The RRAM includes a RRAM bottom metal electrode, a variable resistance dielectric layer arranged over the RRAM bottom metal electrode, and a RRAM top metal electrode arranged over the variable resistance dielectric layer. A capping layer is arranged over the RRAM top metal electrode. A lower surface of the capping layer and an upper surface of the RRAM top metal electrode meet at an interface. Protective sidewalls are adjacent to outer sidewalls of the RRAM top metal electrode. The protective sidewalls have upper surfaces at least substantially aligned to the interface at which the upper surface of the RRAM top metal electrode meets the lower surface of the capping layer.
Abstract translation: 一些实施例涉及电阻随机存取存储器（RRAM）。 RRAM包括RRAM底部金属电极，布置在RRAM底部金属电极上的可变电阻介电层和布置在可变电阻介电层上的RRAM顶部金属电极。 在RRAM顶部金属电极上设置覆盖层。 覆盖层的下表面和RRAM顶部金属电极的上表面在界面处相遇。 保护侧壁与RRAM顶部金属电极的外侧壁相邻。 保护侧壁的上表面至少基本上与RRAM顶部金属电极的上表面与覆盖层的下表面相接触的界面对齐。
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公开(公告)号：US11038010B2
公开(公告)日：2021-06-15
申请号：US14609159
申请日：2015-01-29
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Jian-Shiou Huang , Chia-Shiung Tsai , Cheng-Yuan Tsai , Hsing-Lien Lin , Yao-Wen Chang
Abstract: A structure includes a semiconductor substrate, a conductor-insulator-conductor capacitor. The conductor-insulator-conductor capacitor is disposed on the semiconductor substrate and includes a first conductor, a nitrogenous dielectric layer and a second conductor. The nitrogenous dielectric layer is disposed on the first conductor and the second conductor is disposed on the nitrogenous dielectric layer.
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公开(公告)号：US10937686B2
公开(公告)日：2021-03-02
申请号：US16517934
申请日：2019-07-22
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Jian-Shiou Huang , Bang-Tai Tang , Chih-Tang Peng , Tai-Chun Huang , Yen-Chun Huang
IPC: H01L21/762 , H01L21/02 , H01L21/8234 , H01L21/84
Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor device having an enhanced gap fill layer in trenches. The present disclosure provides a novel gap fill layer formed using a multi-step deposition and in-situ treatment process. The deposition process can be a flowable chemical vapor deposition (FCVD) utilizing one or more assist gases and molecules of low reactive sticking coefficient (RSC). The treatment process can be an in-situ process after the deposition process and includes exposing the deposited gap fill layer to plasma activated assist gas. The assist gas can be formed of ammonia. The low RSC molecule can be formed of trisilylamin (TSA) or perhydropolysilazane (PHPS).
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Patent Agency Ranking
公开(公告)号：US20160268506A1
公开(公告)日：2016-09-15
申请号：US14645932
申请日：2015-03-12
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Jian-Shiou Huang , Cheng-Yuan Tsai , Yao-Wen Chang
IPC: H01L45/00
CPC classification number: H01L45/16 , H01L45/08 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/1675
Abstract: An integrated circuit with a multilayer bottom electrode, and a corresponding method for manufacturing the integrated circuit, are provided. An insulating layer includes an opening, and a bottom electrode substantially fills the opening. The bottom electrode includes a plurality of layers laterally or vertically stacked upon each other, and lining the opening. The layers of the plurality include corresponding surfaces facing an interior of the opening and extending perpendicular or incident to a top surface of the bottom electrode. Further, the layers of the plurality include corresponding regions of increased resistance or height extending along the corresponding surfaces. A dielectric layer is arranged over the insulating layer and the bottom electrode, and a top electrode arranged over the dielectric layer.
Abstract translation: 提供了具有多层底电极的集成电路及其制造方法。 绝缘层包括开口，底部电极基本上填充开口。 底部电极包括彼此横向或垂直堆叠的多个层，并且衬里该开口。 多个层包括面向开口内部并且垂直或入射到底部电极顶表面的对应表面。 此外，多个层包括相应的沿着相应表面延伸的电阻或高度的对应区域。 电介质层设置在绝缘层和底电极之上，以及布置在电介质层上的顶电极。
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公开(公告)号：US20160020390A1
公开(公告)日：2016-01-21
申请号：US14332577
申请日：2014-07-16
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yao-Wen Chang , Jian-Shiou Huang , Hsing-Lien Lin , Cheng-Yuan Tsai , Chia-Shiung Tsai
IPC: H01L45/00
CPC classification number: H01L45/1253 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/16
Abstract: Some embodiments relate to a resistive random access memory (RRAM). The RRAM includes a RRAM bottom metal electrode, a variable resistance dielectric layer arranged over the RRAM bottom metal electrode, and a RRAM top metal electrode arranged over the variable resistance dielectric layer. A capping layer is arranged over the RRAM top metal electrode. A lower surface of the capping layer and an upper surface of the RRAM top metal electrode meet at an interface. Protective sidewalls are adjacent to outer sidewalls of the RRAM top metal electrode. The protective sidewalls have upper surfaces at least substantially aligned to the interface at which the upper surface of the RRAM top metal electrode meets the lower surface of the capping layer.
Abstract translation: 一些实施例涉及电阻随机存取存储器（RRAM）。 RRAM包括RRAM底部金属电极，布置在RRAM底部金属电极上的可变电阻介电层和布置在可变电阻介电层上的RRAM顶部金属电极。 在RRAM顶部金属电极上设置覆盖层。 覆盖层的下表面和RRAM顶部金属电极的上表面在界面处相遇。 保护侧壁与RRAM顶部金属电极的外侧壁相邻。 保护侧壁的上表面至少基本上与RRAM顶部金属电极的上表面与覆盖层的下表面相接触的界面对齐。
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8.发明申请MIM/RRAM Structure with Improved Capacitance and Reduced Leakage Current 有权具有改善电容和降低泄漏电流的MIM / RRAM结构公开(公告)号：US20150380477A1
公开(公告)日：2015-12-31
申请号：US14316910
申请日：2014-06-27
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Jian-Shiou Huang , Yao-Wen Chang , Hsing-Lien Lin , Cheng-Yuan Tsai , Chia-Shiung Tsai
CPC classification number: H01L28/40 , H01L21/02112 , H01L21/0214 , H01L21/02164 , H01L21/0217 , H01L21/02178 , H01L21/02181 , H01L21/02266 , H01L23/5223 , H01L29/88 , H01L45/08 , H01L45/10
Abstract: Some embodiments of the present disclosure provide an integrated circuit (IC) device including a metal-insulator-metal (MIM) capacitor structure. The MIM capacitor structure includes a lower metal capacitor electrode, an upper metal capacitor electrode, and a capacitor dielectric separating the lower metal capacitor electrode from the upper metal capacitor electrode. The capacitor dielectric is made up of an amorphous oxide/nitride matrix and a plurality of metal or metal oxide/nitride nano-particles that are randomly distributed over the volume of amorphous oxide/nitride matrix.
Abstract translation: 本公开的一些实施例提供了包括金属 - 绝缘体 - 金属（MIM）电容器结构的集成电路（IC）装置。 MIM电容器结构包括下金属电容器电极，上金属电容器电极和将下金属电容器电极与上金属电容器电极分离的电容器电介质。 电容器电介质由无定形氧化物/氮化物基体和随机分布在无定形氧化物/氮化物基体的体积上的多个金属或金属氧化物/氮化物纳米颗粒构成。
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公开(公告)号：US20190341294A1
公开(公告)日：2019-11-07
申请号：US16517934
申请日：2019-07-22
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Jian-Shiou Huang , Bang-Tai Tang , Chih-Tang Peng , Tai-Chun Huang , Yen-Chun Huang
IPC: H01L21/762 , H01L21/02 , H01L21/8234
Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor device having an enhanced gap fill layer in trenches. The present disclosure provides a novel gap fill layer formed using a multi-step deposition and in-situ treatment process. The deposition process can be a flowable chemical vapor deposition (FCVD) utilizing one or more assist gases and molecules of low reactive sticking coefficient (RSC). The treatment process can be an in-situ process after the deposition process and includes exposing the deposited gap fill layer to plasma activated assist gas. The assist gas can be formed of ammonia. The low RSC molecule can be formed of trisilylamin (TSA) or perhydropolysilazane (PHPS).
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公开(公告)号：US20190006228A1
公开(公告)日：2019-01-03
申请号：US15876583
申请日：2018-01-22
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Jian-Shiou Huang , Bang-Tai Tang , Chih-Tang Peng , Tai-Chun Huang , Yen-Chun Huang
IPC: H01L21/762 , H01L21/02 , H01L21/8234
CPC classification number: H01L21/76224 , H01L21/0217 , H01L21/02219 , H01L21/02222 , H01L21/02271 , H01L21/02274 , H01L21/0228 , H01L21/02329 , H01L21/0234 , H01L21/823431 , H01L21/823437 , H01L21/823481
Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor device having an enhanced gap fill layer in trenches. The present disclosure provides a novel gap fill layer formed using a multi-step deposition and in-situ treatment process. The deposition process can be a flowable chemical vapor deposition (FCVD) utilizing one or more assist gases and molecules of low reactive sticking coefficient (RSC). The treatment process can be an in-situ process after the deposition process and includes exposing the deposited gap fill layer to plasma activated assist gas. The assist gas can be formed of ammonia. The low RSC molecule can be formed of trisilylamin (TSA) or perhydropolysilazane (PHPS).
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