公开(公告)号：US20240397698A1

公开(公告)日：2024-11-28

申请号：US18789468

申请日：2024-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： You-Cheng XIAO ,  Jhih-Siang HU ,  Ru-Yu WANG ,  Jung-Hsuan CHEN ,  Ting-Wei CHIANG

IPC: H10B10/00 ,  H01L23/528

Abstract: A method includes: abutting a first logic cell having a first cell height to a first memory cell having the first cell height; forming a first conductive rail and a second conductive rail at opposite sides of the first memory cell, respectively; forming a plurality of first conductive rails between the first conductive rail and the second conductive rail; forming a third conductive rail and a fourth conductive rail at opposite sides of the first logic cell, respectively; and forming a plurality of second conductive rails between the third conductive rail and the fourth conductive rail. An amount of the plurality of second conductive rails is larger than an amount of the plurality of first conductive rails.

公开(公告)号：US20230111939A1

公开(公告)日：2023-04-13

申请号：US18064777

申请日：2022-12-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： You-Cheng XIAO ,  Jhih-Siang HU ,  Ru-Yu WANG ,  Jung-Hsuan CHEN ,  Ting-Wei CHIANG

IPC: H01L29/06 ,  H01L23/528

Abstract: A method includes: abutting a first logic cell having a first cell height to a first memory cell having the first cell height; forming a first conductive rail and a second conductive rail at opposite sides of the first memory cell, respectively; forming a plurality of first conductive rails between the first conductive rail and the second conductive rail; forming a third conductive rail and a fourth conductive rail at opposite sides of the first logic cell, respectively; and forming a plurality of second conductive rails between the third conductive rail and the fourth conductive rail. An amount of the plurality of second conductive rails is larger than an amount of the plurality of first conductive rails.

公开(公告)号：US20200227095A1

公开(公告)日：2020-07-16

申请号：US16830935

申请日：2020-03-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Huei CHEN ,  Chien Chi Linus TIEN ,  Kao-Cheng LIN ,  Jung-Hsuan CHEN

IPC: G11C7/06 ,  H01L21/28 ,  G11C11/419 ,  H01L21/8234 ,  H01L23/528 ,  H01L23/552 ,  H01L27/02 ,  H01L27/088 ,  H01L27/11 ,  H01L29/06

Abstract: A sense amplifier (SA) includes a semiconductor substrate having a source/drain (S/D) diffusion region; a pair of SA sensing devices both disposed in the S/D diffusion region; an SA enabling device disposed in the same S/D diffusion region as where the pair of SA sensing devices are disposed in; and a sense amplifier enabling signal (SAE) line for carrying an SAE signal, for turning on the SA enabling device to discharge one of the pair of SA sensing devices during a data read from the sense amplifier, wherein the SA enabling device is arranged to provide buffer protection for source/drain terminals of the pair of SA sensing devices.

公开(公告)号：US20220102363A1

公开(公告)日：2022-03-31

申请号：US17035438

申请日：2020-09-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： You-Cheng XIAO ,  Jhih-Siang HU ,  Ru-Yu WANG ,  Jung-Hsuan CHEN ,  Ting-Wei CHIANG

IPC: H01L27/11 ,  H01L23/528

Abstract: A semiconductor device includes at least one memory cell and at least one logic cell. The at least one logic cell is disposed next to the at least one memory cell and includes a plurality of fins. The plurality of fins are separated into a plurality of fin groups for forming transistors. A distance between two adjacent groups of the plurality of fin groups is different from a distance between another two adjacent groups of the plurality of fin groups. A method is also disclosed herein.

公开(公告)号：US20240021613A1

公开(公告)日：2024-01-18

申请号：US18362755

申请日：2023-07-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Pin-Dai SUE ,  Tzung-Yo HUNG ,  Jung-Hsuan CHEN ,  Ting-Wei CHIANG

IPC: H01L27/088 ,  H01L23/528 ,  H01L21/822 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L23/528 ,  H01L21/8221 ,  H01L21/823431 ,  H01L21/823475 ,  H01L29/66545 ,  H01L21/823437

Abstract: A semiconductor device includes a first transistor disposed over a substrate, a second transistor disposed over the first transistor, and a conductive trace. The first transistor includes first conductive segments, corresponding to drain and source terminals of the first transistor and extending in a first direction, on a first layer. The second transistor includes second conductive segments, corresponding to drain and source terminals of the second transistor and extending in the first direction, on a second layer above the first layer. The conductive trace extends on a third layer. The first to third layers are separated from each other in the first direction, and the third layer is interposed between the first and second layers. The first conductive segments, the second conductive segments, and the conductive trace overlap in a layout view.

公开(公告)号：US20150118803A1

公开(公告)日：2015-04-30

申请号：US14589009

申请日：2015-01-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsien-Yu PAN ,  Jung-Hsuan CHEN ,  Shao-Yu CHOU ,  Yen-Huei CHEN ,  Hung-Jen LIAO

IPC: H01L27/11 ,  H01L21/768 ,  H01L27/02

CPC classification number: H01L27/1116 ,  H01L21/768 ,  H01L27/0207 ,  H01L27/11 ,  H01L2027/11887

Abstract: A method and layout for forming word line decoder devices and other devices having word line decoder cells provides for forming metal interconnect layers using non-DPL photolithography operations and provides for stitching distally disposed transistors using a lower or intermediate metal layer or a subjacent conductive material. The transistors may be disposed in or adjacent longitudinally arranged word line decoder or other cells and the conductive coupling using the metal or conductive material lowers gate resistance between transistors and avoids RC signal delays.

Abstract translation: 用于形成字线解码器装置和具有字线解码器单元的其它装置的方法和布局提供了使用非DPL光刻操作形成金属互连层，并且使用下部或中间金属层或下部导电材料提供了用于缝合的远端布置的晶体管。 晶体管可以设置在纵向布置的字线解码器或其他单元中或其附近，并且使用金属或导电材料的导电耦合降低晶体管之间的栅极电阻并避免RC信号延迟。

公开(公告)号：US20230124337A1

公开(公告)日：2023-04-20

申请号：US18066733

申请日：2022-12-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： You-Cheng XIAO ,  Jhih-Siang HU ,  Ru-Yu WANG ,  Jung-Hsuan CHEN ,  Ting-Wei CHIANG

IPC: H10B10/00 ,  H01L23/528

Abstract: A semiconductor device includes at least one memory cell and at least one logic cell. The at least one logic cell is disposed next to the at least one memory cell. The at least one logic cell includes fins. The fins are separated into fin groups for forming transistors. A distance between two adjacent groups of the plurality of fin groups is different from a distance between another two adjacent groups of the plurality of fin groups.

公开(公告)号：US20180330765A1

公开(公告)日：2018-11-15

申请号：US16042894

申请日：2018-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Huei CHEN ,  Chien Chi Linus TIEN ,  Kao-Cheng LIN ,  Jung-Hsuan CHEN

IPC: G11C7/06 ,  H01L29/06 ,  H01L27/11 ,  H01L23/552 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/02 ,  G11C11/419 ,  H01L23/528 ,  H01L21/20 ,  H01L27/092

CPC classification number: G11C7/065 ,  G11C11/419 ,  H01L21/20 ,  H01L21/2003 ,  H01L21/28008 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/528 ,  H01L23/552 ,  H01L27/0207 ,  H01L27/0296 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1104 ,  H01L29/0649

Abstract: A sense amplifier (SA) comprises a semiconductor substrate having an oxide definition (OD) region, a pair of SA sensing devices, a SA enabling device, and a sense amplifier enabling signal (SAE) line for carrying an SAE signal. The pair of SA sensing devices have the same poly gate length Lg as the SA enabling device, and they all share the same OD region. When enabled, the SAE signal turns on the SA enabling device to discharge one of the pair of SA sensing devices for data read from the sense amplifier.

公开(公告)号：US20140073124A1

公开(公告)日：2014-03-13

申请号：US14079671

申请日：2013-11-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Huei CHEN ,  Jung-Hsuan CHEN ,  Shao-Yu CHOU ,  Hung-Jen LIAO ,  Li-Chun TIEN

IPC: H01L21/28

CPC classification number: H01L21/28008 ,  H01L21/28123 ,  H01L21/823425 ,  H01L21/823481 ,  H01L27/0207 ,  H01L29/66628 ,  H01L29/7848

Abstract: A method includes forming a first plurality of fingers over an active area of a semiconductor substrate. Each of the first plurality of fingers has a respective length that extends in a direction that is parallel to width direction of the active area. The first plurality of fingers form at least one gate of at least one transistor having a source and a drain formed by a portion of the active area. A first dummy polysilicon structure is formed over a portion of the active area between an outer one of the first plurality of fingers and a first edge of the semiconductor substrate. A second dummy polysilicon structure is over the semiconductor substrate between the first dummy polysilicon structure and the first edge of the semiconductor substrate.

Abstract translation: 一种方法包括在半导体衬底的有效区域上形成第一多个指状物。 第一多个指状物中的每一个具有在与有源区域的宽度方向平行的方向上延伸的相应长度。 第一多个指状物形成至少一个晶体管的至少一个栅极，该晶体管具有由有源区域的一部分形成的源极和漏极。 第一虚设多晶硅结构形成在第一多个指状物的外部之一和半导体衬底的第一边缘之间的有源区域的一部分上。 第二虚设多晶硅结构在第一虚设多晶硅结构和半导体衬底的第一边缘之间的半导体衬底之上。

公开(公告)号：US20240397697A1

公开(公告)日：2024-11-28

申请号：US18789448

申请日：2024-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： You-Cheng XIAO ,  Jhih-Siang HU ,  Ru-Yu WANG ,  Jung-Hsuan CHEN ,  Ting-Wei CHIANG

IPC: H10B10/00 ,  H01L23/528

Abstract: A semiconductor device includes at least one memory cell and at least one logic cell. The at least one logic cell is disposed next to the at least one memory cell. The at least one logic cell includes fins. The fins are separated into fin groups for forming transistors. A distance between two adjacent groups of the plurality of fin groups is different from a distance between another two adjacent groups of the plurality of fin groups.