公开(公告)号：US09851915B2

公开(公告)日：2017-12-26

申请号：US15627837

申请日：2017-06-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuang Ting Chen ,  Ching-Wei Wu

IPC: G06F12/00 ,  G06F13/00 ,  G06F3/06 ,  G11C7/18 ,  G11C7/10 ,  G11C5/06 ,  G11C5/02 ,  H01L27/06 ,  H01L27/11

CPC classification number: G06F3/0625 ,  G06F3/0665 ,  G06F3/0689 ,  G11C5/025 ,  G11C5/063 ,  G11C5/066 ,  G11C7/1075 ,  G11C7/18 ,  G11C2207/108 ,  G11C2207/2209 ,  G11C2211/4016 ,  H01L27/0688 ,  H01L27/1104

Abstract: A memory device includes a first group of memory cells, a second group of memory cells, a third group of memory cells, and a fourth group of memory cells. A control circuit performs a first read/write operation during a first time interval by writing a first data value to the first group while concurrently reading a second data value from the second group. The control circuit performs a second read/write operation during a second time interval, which is after the first time interval, by writing a third data value to the third group while concurrently reading a fourth data value from the fourth group. The first and third data values are collectively made up of N-bits and collectively correspond to an N-bit input data word provided onto input pins of the memory device prior to the first time interval.

公开(公告)号：US20170285990A1

公开(公告)日：2017-10-05

申请号：US15627837

申请日：2017-06-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuang Ting Chen ,  Ching-Wei Wu

IPC: G06F3/06 ,  G11C5/02 ,  G11C5/06 ,  G11C7/18 ,  G11C7/10

CPC classification number: G06F3/0625 ,  G06F3/0665 ,  G06F3/0689 ,  G11C5/025 ,  G11C5/063 ,  G11C5/066 ,  G11C7/1075 ,  G11C7/18 ,  G11C2207/108 ,  G11C2207/2209 ,  G11C2211/4016 ,  H01L27/0688 ,  H01L27/1104

Abstract: A memory device includes a first group of memory cells, a second group of memory cells, a third group of memory cells, and a fourth group of memory cells. A control circuit performs a first read/write operation during a first time interval by writing a first data value to the first group while concurrently reading a second data value from the second group. The control circuit performs a second read/write operation during a second time interval, which is after the first time interval, by writing a third data value to the third group while concurrently reading a fourth data value from the fourth group. The first and third data values are collectively made up of N-bits and collectively correspond to an N-bit input data word provided onto input pins of the memory device prior to the first time interval.

公开(公告)号：US09690510B2

公开(公告)日：2017-06-27

申请号：US14259607

申请日：2014-04-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuang Ting Chen ,  Ching-Wei Wu

IPC: G06F13/00 ,  G06F3/06 ,  G11C5/02 ,  G11C5/06 ,  G11C7/10 ,  G11C7/18 ,  H01L27/06 ,  H01L27/11

CPC classification number: G06F3/0625 ,  G06F3/0665 ,  G06F3/0689 ,  G11C5/025 ,  G11C5/063 ,  G11C5/066 ,  G11C7/1075 ,  G11C7/18 ,  G11C2207/108 ,  G11C2207/2209 ,  G11C2211/4016 ,  H01L27/0688 ,  H01L27/1104

Abstract: Some embodiments of the present disclosure relate to a memory device wherein a single memory cell array is partitioned between two or more tiers which are vertically integrated on a single substrate. The memory device also includes support circuitry including a control circuit configured to read and write data to the memory cells on each tier, and a shared input/output (I/O) architecture which is connected the memory cells within each tier and configured to receive input data word prior to a write operation, and further configured to provide output data word after a read operation. Other devices and methods are also disclosed.

公开(公告)号：US09281311B2

公开(公告)日：2016-03-08

申请号：US14031057

申请日：2013-09-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Wei Wu ,  Wei-Shuo Kao ,  Chia-Cheng Chen ,  Kuang Ting Chen

IPC: H01L27/108 ,  H01L29/94 ,  H01L27/11 ,  G11C7/12 ,  G11C7/18 ,  G11C11/419 ,  G11C11/412

CPC classification number: H01L27/1116 ,  G11C7/12 ,  G11C7/18 ,  G11C11/412 ,  G11C11/419 ,  G11C2207/005 ,  H01L29/94

Abstract: An integrated circuit includes a plurality of metal layers of bit cells of a memory cell array disposed in a first metal layer and extending in a first direction, a plurality of word lines of the memory cell array disposed in a second metal layer and extending in a second direction that is different from the first direction, and at least two conductive traces disposed in a third metal layer substantially adjacent to each other and extending at least partially across the memory cell array, a first one of the at least two conductive traces coupled to a driving source node of a write assist circuit, and a second conductive trace of the at least two conductive traces coupled to an enable input of the write-assist circuit, where the at least two conductive traces form at least one embedded capacitor having a capacitive coupling to the bit line.

Abstract translation: 一种集成电路包括设置在第一金属层中并沿第一方向延伸的存储单元阵列的位单元的多个金属层，所述存储单元阵列的多个字线设置在第二金属层中并在 与第一方向不同的第二方向，以及布置在基本上彼此相邻并且至少部分地跨过存储单元阵列延伸的第三金属层中的至少两个导电迹线，所述至少两个导电迹线中的第一导电迹线耦合到 写辅助电路的驱动源节点和耦合到写辅助电路的使能输入的至少两个导电迹线的第二导电迹线，其中所述至少两个导电迹线形成至少一个嵌入式电容器，其具有电容 耦合到位线。

公开(公告)号：US20150309750A1

公开(公告)日：2015-10-29

申请号：US14259607

申请日：2014-04-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuang Ting Chen ,  Ching-Wei Wu

IPC: G06F3/06 ,  G11C11/406

CPC classification number: G06F3/0625 ,  G06F3/0665 ,  G06F3/0689 ,  G11C5/025 ,  G11C5/063 ,  G11C5/066 ,  G11C7/1075 ,  G11C7/18 ,  G11C2207/108 ,  G11C2207/2209 ,  G11C2211/4016 ,  H01L27/0688 ,  H01L27/1104

Abstract: Some embodiments of the present disclosure relate to a memory device wherein a single memory cell array is partitioned between two or more tiers which are vertically integrated on a single substrate. The memory device also includes support circuitry including a control circuit configured to read and write data to the memory cells on each tier, and a shared input/output (I/O) architecture which is connected the memory cells within each tier and configured to receive input data word prior to a write operation, and further configured to provide output data word after a read operation. Other devices and methods are also disclosed.

Abstract translation: 本公开的一些实施例涉及一种存储器件，其中单个存储器单元阵列在垂直集成在单个衬底上的两个或更多个层之间分隔。 该存储设备还包括支持电路，其包括配置成将数据读取和写入每层上的存储器单元的控制电路，以及共享输入/输出（I / O）架构，其连接每层内的存储器单元并被配置为接收 在写入操作之前的输入数据字，并且还被配置为在读取操作之后提供输出数据字。 还公开了其它装置和方法。