公开(公告)号：US20230387259A1

公开(公告)日：2023-11-30

申请号：US18446998

申请日：2023-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-An Lin ,  Kuo-Pi Tseng ,  Tzu-Chieh Su

IPC: H01L29/66 ,  H01L21/3065 ,  H01L29/08 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L29/66636 ,  H01L21/3065 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: Source and drain formation techniques disclosed herein provide FinFETs with reduced channel resistance and reduced drain-induced barrier lowering. An exemplary three-step etch method for forming a source/drain recess in a source/drain region of a fin includes a first anisotropic etch, an isotropic etch, and a second anisotropic etch. The first anisotropic etch and the isotropic etch are tuned to define a location of a source/drain tip. A depth of the source/drain recess after the first anisotropic etch and the isotropic etch is less than a target depth. The second anisotropic etch is tuned to extend the depth of the source/drain recess to the target depth. The source/drain tip is near a top of the fin to reduce channel resistance while a bottom portion of the source/drain recess is spaced a distance from a gate footing that can minimize DIBL. The source/drain recess is filled with an epitaxial semiconductor material.

公开(公告)号：US11489062B2

公开(公告)日：2022-11-01

申请号：US16867949

申请日：2020-05-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-An Lin ,  Kuo-Pi Tseng ,  Tzu-Chieh Su

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/417 ,  H01L21/3065

Abstract: Source and drain formation techniques are disclosed herein. An exemplary three-step etch method for forming a source/drain recess in a source/drain region of a fin includes a first anisotropic etch, an isotropic etch, and a second anisotropic etch. The first anisotropic etch and the isotropic etch are tuned to define a location of a source/drain tip. A depth of the source/drain recess after the first anisotropic etch and the isotropic etch is less than a target depth. The second anisotropic etch is tuned to extend the depth of the source/drain recess to the target depth. The source/drain tip is near a top of the fin while a bottom portion of the source/drain recess is spaced a distance from a gate footing. The source/drain recess is filled with an epitaxial semiconductor material.

公开(公告)号：US20200381537A1

公开(公告)日：2020-12-03

申请号：US16867949

申请日：2020-05-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-An Lin ,  Kuo-Pi Tseng ,  Tzu-Chieh Su

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/417 ,  H01L21/3065

Abstract: Source and drain formation techniques disclosed herein provide FinFETs with reduced channel resistance and reduced drain-induced barrier lowering. An exemplary three-step etch method for forming a source/drain recess in a source/drain region of a fin includes a first anisotropic etch, an isotropic etch, and a second anisotropic etch. The first anisotropic etch and the isotropic etch are tuned to define a location of a source/drain tip. A depth of the source/drain recess after the first anisotropic etch and the isotropic etch is less than a target depth. The second anisotropic etch is tuned to extend the depth of the source/drain recess to the target depth. The source/drain tip is near a top of the fin to reduce channel resistance while a bottom portion of the source/drain recess is spaced a distance from a gate footing that can minimize DIBL. The source/drain recess is filled with an epitaxial semiconductor material.

公开(公告)号：US11824102B2

公开(公告)日：2023-11-21

申请号：US17978576

申请日：2022-11-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-An Lin ,  Kuo-Pi Tseng ,  Tzu-Chieh Su

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L21/3065 ,  H01L29/417

CPC classification number: H01L29/66636 ,  H01L21/3065 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: Source and drain formation techniques disclosed herein provide FinFETs with reduced channel resistance and reduced drain-induced barrier lowering. An exemplary three-step etch method for forming a source/drain recess in a source/drain region of a fin includes a first anisotropic etch, an isotropic etch, and a second anisotropic etch. The first anisotropic etch and the isotropic etch are tuned to define a location of a source/drain tip. A depth of the source/drain recess after the first anisotropic etch and the isotropic etch is less than a target depth. The second anisotropic etch is tuned to extend the depth of the source/drain recess to the target depth. The source/drain tip is near a top of the fin to reduce channel resistance while a bottom portion of the source/drain recess is spaced a distance from a gate footing that can minimize DIBL. The source/drain recess is filled with an epitaxial semiconductor material.

公开(公告)号：US20230050300A1

公开(公告)日：2023-02-16

申请号：US17978576

申请日：2022-11-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-An Lin ,  Kuo-Pi Tseng ,  Tzu-Chieh Su

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L21/3065 ,  H01L29/417

Abstract: Source and drain formation techniques disclosed herein provide FinFETs with reduced channel resistance and reduced drain-induced barrier lowering. An exemplary three-step etch method for forming a source/drain recess in a source/drain region of a fin includes a first anisotropic etch, an isotropic etch, and a second anisotropic etch. The first anisotropic etch and the isotropic etch are tuned to define a location of a source/drain tip. A depth of the source/drain recess after the first anisotropic etch and the isotropic etch is less than a target depth. The second anisotropic etch is tuned to extend the depth of the source/drain recess to the target depth. The source/drain tip is near a top of the fin to reduce channel resistance while a bottom portion of the source/drain recess is spaced a distance from a gate footing that can minimize DIBL. The source/drain recess is filled with an epitaxial semiconductor material.