公开(公告)号：US20230387259A1

公开(公告)日：2023-11-30

申请号：US18446998

申请日：2023-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-An Lin ,  Kuo-Pi Tseng ,  Tzu-Chieh Su

IPC: H01L29/66 ,  H01L21/3065 ,  H01L29/08 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L29/66636 ,  H01L21/3065 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: Source and drain formation techniques disclosed herein provide FinFETs with reduced channel resistance and reduced drain-induced barrier lowering. An exemplary three-step etch method for forming a source/drain recess in a source/drain region of a fin includes a first anisotropic etch, an isotropic etch, and a second anisotropic etch. The first anisotropic etch and the isotropic etch are tuned to define a location of a source/drain tip. A depth of the source/drain recess after the first anisotropic etch and the isotropic etch is less than a target depth. The second anisotropic etch is tuned to extend the depth of the source/drain recess to the target depth. The source/drain tip is near a top of the fin to reduce channel resistance while a bottom portion of the source/drain recess is spaced a distance from a gate footing that can minimize DIBL. The source/drain recess is filled with an epitaxial semiconductor material.

公开(公告)号：US20230261080A1

公开(公告)日：2023-08-17

申请号：US18297922

申请日：2023-04-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Kai Lin ,  Tzu-Chieh Su ,  Che-Hao Chang

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/42392 ,  H01L29/78696 ,  H01L29/0665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/66553

Abstract: A method includes forming a stack of layers comprising a plurality of semiconductor nanostructures, and a plurality of sacrificial layers. The plurality of semiconductor nanostructures and the plurality of sacrificial layers are arranged alternatingly. The method further includes laterally recessing the plurality of sacrificial layers to form lateral recesses, depositing a first spacer layer extending into the lateral recesses, with the first spacer layer comprising a first dielectric material, depositing a second spacer layer on the first spacer layer, with the second spacer layer comprising a second dielectric material different from the first dielectric material, and trimming the first spacer layer and the second spacer layer to form inner spacers.

公开(公告)号：US11489062B2

公开(公告)日：2022-11-01

申请号：US16867949

申请日：2020-05-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-An Lin ,  Kuo-Pi Tseng ,  Tzu-Chieh Su

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/417 ,  H01L21/3065

Abstract: Source and drain formation techniques are disclosed herein. An exemplary three-step etch method for forming a source/drain recess in a source/drain region of a fin includes a first anisotropic etch, an isotropic etch, and a second anisotropic etch. The first anisotropic etch and the isotropic etch are tuned to define a location of a source/drain tip. A depth of the source/drain recess after the first anisotropic etch and the isotropic etch is less than a target depth. The second anisotropic etch is tuned to extend the depth of the source/drain recess to the target depth. The source/drain tip is near a top of the fin while a bottom portion of the source/drain recess is spaced a distance from a gate footing. The source/drain recess is filled with an epitaxial semiconductor material.

公开(公告)号：US20200381537A1

公开(公告)日：2020-12-03

申请号：US16867949

申请日：2020-05-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-An Lin ,  Kuo-Pi Tseng ,  Tzu-Chieh Su

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/417 ,  H01L21/3065

Abstract: Source and drain formation techniques disclosed herein provide FinFETs with reduced channel resistance and reduced drain-induced barrier lowering. An exemplary three-step etch method for forming a source/drain recess in a source/drain region of a fin includes a first anisotropic etch, an isotropic etch, and a second anisotropic etch. The first anisotropic etch and the isotropic etch are tuned to define a location of a source/drain tip. A depth of the source/drain recess after the first anisotropic etch and the isotropic etch is less than a target depth. The second anisotropic etch is tuned to extend the depth of the source/drain recess to the target depth. The source/drain tip is near a top of the fin to reduce channel resistance while a bottom portion of the source/drain recess is spaced a distance from a gate footing that can minimize DIBL. The source/drain recess is filled with an epitaxial semiconductor material.

公开(公告)号：US11824102B2

公开(公告)日：2023-11-21

申请号：US17978576

申请日：2022-11-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-An Lin ,  Kuo-Pi Tseng ,  Tzu-Chieh Su

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L21/3065 ,  H01L29/417

CPC classification number: H01L29/66636 ,  H01L21/3065 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: Source and drain formation techniques disclosed herein provide FinFETs with reduced channel resistance and reduced drain-induced barrier lowering. An exemplary three-step etch method for forming a source/drain recess in a source/drain region of a fin includes a first anisotropic etch, an isotropic etch, and a second anisotropic etch. The first anisotropic etch and the isotropic etch are tuned to define a location of a source/drain tip. A depth of the source/drain recess after the first anisotropic etch and the isotropic etch is less than a target depth. The second anisotropic etch is tuned to extend the depth of the source/drain recess to the target depth. The source/drain tip is near a top of the fin to reduce channel resistance while a bottom portion of the source/drain recess is spaced a distance from a gate footing that can minimize DIBL. The source/drain recess is filled with an epitaxial semiconductor material.

公开(公告)号：US20230050300A1

公开(公告)日：2023-02-16

申请号：US17978576

申请日：2022-11-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-An Lin ,  Kuo-Pi Tseng ,  Tzu-Chieh Su

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L21/3065 ,  H01L29/417

Abstract: Source and drain formation techniques disclosed herein provide FinFETs with reduced channel resistance and reduced drain-induced barrier lowering. An exemplary three-step etch method for forming a source/drain recess in a source/drain region of a fin includes a first anisotropic etch, an isotropic etch, and a second anisotropic etch. The first anisotropic etch and the isotropic etch are tuned to define a location of a source/drain tip. A depth of the source/drain recess after the first anisotropic etch and the isotropic etch is less than a target depth. The second anisotropic etch is tuned to extend the depth of the source/drain recess to the target depth. The source/drain tip is near a top of the fin to reduce channel resistance while a bottom portion of the source/drain recess is spaced a distance from a gate footing that can minimize DIBL. The source/drain recess is filled with an epitaxial semiconductor material.