公开(公告)号：US12002854B2

公开(公告)日：2024-06-04

申请号：US17520983

申请日：2021-11-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Heng-Wen Ting ,  Kei-Wei Chen ,  Chii-Horng Li ,  Pei-Ren Jeng ,  Hsueh-Chang Sung ,  Yen-Ru Lee ,  Chun-An Lin

IPC: H01L29/08 ,  H01L21/02 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L21/02532 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/785

Abstract: A semiconductor device having an improved source/drain region profile and a method for forming the same are disclosed. In an embodiment, a method includes etching one or more semiconductor fins to form one or more recesses; and forming a source/drain region in the one ore more recesses, the forming the source/drain region including epitaxially growing a first semiconductor material in the one or more recesses at a temperature of 600° C. to 800° C., the first semiconductor material including doped silicon germanium; and conformally depositing a second semiconductor material over the first semiconductor material at a temperature of 300° C. to 600° C., the second semiconductor material including doped silicon germanium and having a different composition than the first semiconductor material.

公开(公告)号：US11961912B2

公开(公告)日：2024-04-16

申请号：US17833356

申请日：2022-06-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-An Lin ,  Wei-Yuan Lu ,  Feng-Cheng Yang ,  Tzu-Ching Lin ,  Li-Li Su

IPC: H01L29/78 ,  A61B5/15 ,  G01N1/14 ,  G01N33/49 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/04

CPC classification number: H01L29/785 ,  A61B5/150099 ,  A61B5/150992 ,  G01N1/14 ,  G01N33/4915 ,  H01L21/02532 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/045 ,  H01L29/7853

Abstract: The present application provides a semiconductor device and the method of making the same. The method includes recessing a fin extending from a substrate, forming a base epitaxial feature on the recessed fin, forming a bar-like epitaxial feature on the base epitaxial feature, and forming a conformal epitaxial feature on the bar-like epitaxial feature. The forming of the bar-like epitaxial feature includes in-situ doping the bar-like epitaxial feature with an n-type dopant at a first doping concentration. The forming of the conformal epitaxial feature includes in-situ doping the conformal epitaxial feature with a second doping concentration greater than the first doping concentration.

公开(公告)号：US20220059655A1

公开(公告)日：2022-02-24

申请号：US17520983

申请日：2021-11-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Heng-Wen Ting ,  Kei-Wei Chen ,  Chii-Horng Li ,  Pei-Ren Jeng ,  Hsueh-Chang Sung ,  Yen-Ru Lee ,  Chun-An Lin

IPC: H01L29/08 ,  H01L29/66 ,  H01L21/02 ,  H01L29/78

Abstract: A semiconductor device having an improved source/drain region profile and a method for forming the same are disclosed. In an embodiment, a method includes etching one or more semiconductor fins to form one or more recesses; and forming a source/drain region in the one ore more recesses, the forming the source/drain region including epitaxially growing a first semiconductor material in the one or more recesses at a temperature of 600° C. to 800° C., the first semiconductor material including doped silicon germanium; and conformally depositing a second semiconductor material over the first semiconductor material at a temperature of 300° C. to 600° C., the second semiconductor material including doped silicon germanium and having a different composition than the first semiconductor material.

公开(公告)号：US20210202733A1

公开(公告)日：2021-07-01

申请号：US17201147

申请日：2021-03-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-An Lin ,  Wei-Yuan Lu ,  Feng-Cheng Yang ,  Tzu-Ching Lin ,  Li-Li Su

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/02 ,  A61B5/15 ,  G01N1/14 ,  G01N33/49

Abstract: The present application provides a semiconductor device and the method of making the same. The method includes recessing a fin extending from a substrate, forming a base epitaxial feature on the recessed fin, forming a bar-like epitaxial feature on the base epitaxial feature, and forming a conformal epitaxial feature on the bar-like epitaxial feature. The forming of the bar-like epitaxial feature includes in-situ doping the bar-like epitaxial feature with an n-type dopant at a first doping concentration. The forming of the conformal epitaxial feature includes in-situ doping the conformal epitaxial feature with a second doping concentration greater than the first doping concentration.

公开(公告)号：US10950730B2

公开(公告)日：2021-03-16

申请号：US16529357

申请日：2019-08-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-An Lin ,  Wei-Yuan Lu ,  Feng-Cheng Yang ,  Tzu-Ching Lin ,  Li-Li Su

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/02 ,  A61B5/15 ,  G01N1/14 ,  G01N33/49 ,  H01L29/04

Abstract: The present application provides a semiconductor device and the method of making the same. The method includes recessing a fin extending from a substrate, forming a base epitaxial feature on the recessed fin, forming a bar-like epitaxial feature on the base epitaxial feature, and forming a conformal epitaxial feature on the bar-like epitaxial feature. The forming of the bar-like epitaxial feature includes in-situ doping the bar-like epitaxial feature with an n-type dopant at a first doping concentration. The forming of the conformal epitaxial feature includes in-situ doping the conformal epitaxial feature with a second doping concentration greater than the first doping concentration.

公开(公告)号：US10276693B1

公开(公告)日：2019-04-30

申请号：US15799385

申请日：2017-10-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-An Lin ,  Chun-Hsiung Lin ,  Chia-Ta Yu ,  Sai-Hooi Yeong ,  Ching-Fang Huang ,  Wen-Hsing Hsieh

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/311 ,  H01L21/3065

Abstract: A semiconductor device includes a substrate, a bottom semiconductor fin, at least one sidewall structure, a top semiconductor fin, and a gate structure. The bottom semiconductor fin is disposed on the substrate. The sidewall structure protrudes from the semiconductor fin. The top semiconductor fin is disposed on the bottom semiconductor fin. The top semiconductor fin includes a channel portion and at least one source/drain portion. The source/drain portion is disposed between the channel portion and the sidewall structure. The gate structure covers the channel portion of the top semiconductor fin.

公开(公告)号：US12125879B2

公开(公告)日：2024-10-22

申请号：US18360495

申请日：2023-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： I-Wen Wu ,  Chen-Ming Lee ,  Fu-Kai Yang ,  Mei-Yun Wang ,  Chun-An Lin ,  Wei-Yuan Lu ,  Guan-Ren Wang ,  Peng Wang

IPC: H01L29/08 ,  H01L21/02 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L21/02532 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of semiconductor fabrication includes providing a semiconductor structure having a substrate and first, second, third, and fourth fins above the substrate. The method further includes forming an n-type epitaxial source/drain (S/D) feature on the first and second fins, forming a p-type epitaxial S/D feature on the third and fourth fins, and performing a selective etch process on the semiconductor structure to remove upper portions of the n-type epitaxial S/D feature and the p-type epitaxial S/D feature such that more is removed from the n-type epitaxial S/D feature than the p-type epitaxial S/D feature.

公开(公告)号：US11784222B2

公开(公告)日：2023-10-10

申请号：US17571822

申请日：2022-01-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： I-Wen Wu ,  Chen-Ming Lee ,  Fu-Kai Yang ,  Mei-Yun Wang ,  Chun-An Lin ,  Wei-Yuan Lu ,  Guan-Ren Wang ,  Peng Wang

IPC: H01L29/08 ,  H01L21/02 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L21/02532 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of semiconductor fabrication includes providing a semiconductor structure having a substrate and first, second, third, and fourth fins above the substrate. The method further includes forming an n-type epitaxial source/drain (S/D) feature on the first and second fins, forming a p-type epitaxial S/D feature on the third and fourth fins, and performing a selective etch process on the semiconductor structure to remove upper portions of the n-type epitaxial S/D feature and the p-type epitaxial S/D feature such that more is removed from the n-type epitaxial S/D feature than the p-type epitaxial S/D feature.

公开(公告)号：US11489062B2

公开(公告)日：2022-11-01

申请号：US16867949

申请日：2020-05-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-An Lin ,  Kuo-Pi Tseng ,  Tzu-Chieh Su

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/417 ,  H01L21/3065

Abstract: Source and drain formation techniques are disclosed herein. An exemplary three-step etch method for forming a source/drain recess in a source/drain region of a fin includes a first anisotropic etch, an isotropic etch, and a second anisotropic etch. The first anisotropic etch and the isotropic etch are tuned to define a location of a source/drain tip. A depth of the source/drain recess after the first anisotropic etch and the isotropic etch is less than a target depth. The second anisotropic etch is tuned to extend the depth of the source/drain recess to the target depth. The source/drain tip is near a top of the fin while a bottom portion of the source/drain recess is spaced a distance from a gate footing. The source/drain recess is filled with an epitaxial semiconductor material.

公开(公告)号：US20200381537A1

公开(公告)日：2020-12-03

申请号：US16867949

申请日：2020-05-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-An Lin ,  Kuo-Pi Tseng ,  Tzu-Chieh Su

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/417 ,  H01L21/3065

Abstract: Source and drain formation techniques disclosed herein provide FinFETs with reduced channel resistance and reduced drain-induced barrier lowering. An exemplary three-step etch method for forming a source/drain recess in a source/drain region of a fin includes a first anisotropic etch, an isotropic etch, and a second anisotropic etch. The first anisotropic etch and the isotropic etch are tuned to define a location of a source/drain tip. A depth of the source/drain recess after the first anisotropic etch and the isotropic etch is less than a target depth. The second anisotropic etch is tuned to extend the depth of the source/drain recess to the target depth. The source/drain tip is near a top of the fin to reduce channel resistance while a bottom portion of the source/drain recess is spaced a distance from a gate footing that can minimize DIBL. The source/drain recess is filled with an epitaxial semiconductor material.