公开(公告)号：US20230197723A1

公开(公告)日：2023-06-22

申请号：US18168065

申请日：2023-02-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ali KESHAVARZI ,  Ta-Pen GUO ,  Shu-Hui SUNG ,  Hsiang-Jen TSENG ,  Shyue-Shyh LIN ,  Lee-Chung LU ,  Chung-Cheng WU ,  Li-Chun TIEN ,  Jung-Chan YANG ,  Ting Yu CHEN ,  Min CAO ,  Yung-Chin HOU

IPC: H01L27/092 ,  H01L21/8238 ,  H01L23/485 ,  H01L27/02 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/49

CPC classification number: H01L27/092 ,  H01L21/823871 ,  H01L23/485 ,  H01L27/0207 ,  H01L29/4238 ,  H01L29/66545 ,  H01L29/7833 ,  H01L29/0649 ,  H01L29/495 ,  H01L2924/0002

Abstract: An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.

公开(公告)号：US20210098625A1

公开(公告)日：2021-04-01

申请号：US16586523

申请日：2019-09-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Wei TSAI ,  Yu-Xuan HUANG ,  Kuan-Lun CHENG ,  Chih-Hao WANG ,  Min CAO ,  Jung-Hung CHANG ,  Lo-Heng CHANG ,  Pei-Hsun WANG ,  Kuo-Cheng CHIANG

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first gate stack and a second gate stack over a substrate. The substrate has a base, a first fin structure, and a second fin structure over the base, the second fin structure is wider than the first fin structure. The method includes partially removing the first fin structure, which is not covered by the first gate stack, and the second fin structure, which is not covered by the second gate stack. The method includes forming an inner spacer layer over the first fin structure, which is not covered by the first gate stack. The method includes forming a first stressor and a second stressor respectively over the inner spacer layer and the second fin structure, which is not covered by the second gate stack.