公开(公告)号：US20230275081A1

公开(公告)日：2023-08-31

申请号：US18313014

申请日：2023-05-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hui-Zhong ZHUANG ,  Xiang-Dong CHEN ,  Lee-Chung LU ,  Tzu-Ying LIN ,  Yung-Chin HOU

IPC: H01L27/02 ,  G06F30/392 ,  H01L27/092 ,  H01L23/528

CPC classification number: H01L27/0207 ,  G06F30/392 ,  H01L27/0924 ,  H01L23/5286

Abstract: A semiconductor device includes first and second cell rows, first to fourth fin shaped structures. The first cell row has a first row height. The second cell row is adjacent with the first cell row, and having a second row height. The first fin shaped structure extends across the first cell row. The second fin shaped structure extends across the first cell row, and separated from the first fin shaped structure. The third fin shaped structure extends across the second cell row. The fourth fin shaped structure extends across the second cell row, and separated from the third fin shaped structure. The first to fourth fin shaped structures are arranged in order along the first direction, each of the first, second and fourth fin shaped structure has a first conductive type, the third fin shaped structure has a second conductive type.

公开(公告)号：US20220384417A1

公开(公告)日：2022-12-01

申请号：US17884293

申请日：2022-08-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hui-Zhong ZHUANG ,  Xiang-Dong CHEN ,  Lee-Chung LU ,  Tzu-Ying LIN ,  Yung-Chin HOU

IPC: H01L27/02 ,  G06F30/392 ,  H01L27/092 ,  H01L23/528

Abstract: A method includes disposing a first power rail, a second power rail and a third power rail arranged in order; disposing a first cell row having a first row height between the first power rail and the second power rail; and disposing a second cell row having the first row height between the third power rail and the second power rail. Each of the first power rail and the third power rail has a first width, and the second power rail has a second width larger than the first width.

公开(公告)号：US20210390240A1

公开(公告)日：2021-12-16

申请号：US17404511

申请日：2021-08-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuang-Hung CHANG ,  Yuan-Te HOU ,  Chung-Hsing WANG ,  Yung-Chin HOU

IPC: G06F30/392 ,  G06F30/20 ,  H01L23/528 ,  H01L27/088 ,  G06F30/394 ,  G06F30/327

Abstract: An IC structure includes first, second, third, and fourth transistors on a substrate, a first net and a second net. The first net includes a plurality of first metal lines routed on a first metallization layer, and a plurality of first metal vias electrically connecting the plurality of first metal lines to the first and second transistors. The second net includes a plurality of second metal lines routed on a second metallization layer, and a plurality of second metal vias electrically connecting the plurality of second metal lines to the third and fourth transistors. A total length of the second metal lines of the second net is shorter than a total length of the first metal lines of the first net. A count of the f first metal vias of the first net is less than a count of the second metal vias of the second net.

公开(公告)号：US20180268096A1

公开(公告)日：2018-09-20

申请号：US15724663

申请日：2017-10-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Lin CHUANG ,  Ching-Fang CHEN ,  Wei-Li CHEN ,  Wei-Pin CHANGCHIEN ,  Yung-Chin HOU ,  Yun-Han LEE

IPC: G06F17/50 ,  G06N99/00

Abstract: Electronic design automation (EDA) of the present disclosure, in various embodiments, optimizes designing, simulating, analyzing, and verifying of one or more electronic architectural designs for an electronic device. The EDA of the present disclosure identifies one or more electronic architectural features from the one or more electronic architectural designs. In some situations, the EDA of the present disclosure can manipulate one or more electronic architectural models over multiple iterations using a machine learning process until one or more electronic architectural models from among the one or more electronic architectural models satisfy one or more electronic design targets. The EDA of the present disclosure substitutes the one or more electronic architectural models that satisfy the one or more electronic design targets for the one or more electronic architectural features in the one or more electronic architectural designs to optimize the one or more electronic architectural designs. The EDA of the present disclosure can substitute the one or more electronic architectural models before, during, and/or after designing, simulating, analyzing, and/or verifying of the one or more electronic architectural designs to effectively decrease the time to market (TTM) for the electronic device.

公开(公告)号：US20230197723A1

公开(公告)日：2023-06-22

申请号：US18168065

申请日：2023-02-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ali KESHAVARZI ,  Ta-Pen GUO ,  Shu-Hui SUNG ,  Hsiang-Jen TSENG ,  Shyue-Shyh LIN ,  Lee-Chung LU ,  Chung-Cheng WU ,  Li-Chun TIEN ,  Jung-Chan YANG ,  Ting Yu CHEN ,  Min CAO ,  Yung-Chin HOU

IPC: H01L27/092 ,  H01L21/8238 ,  H01L23/485 ,  H01L27/02 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/49

CPC classification number: H01L27/092 ,  H01L21/823871 ,  H01L23/485 ,  H01L27/0207 ,  H01L29/4238 ,  H01L29/66545 ,  H01L29/7833 ,  H01L29/0649 ,  H01L29/495 ,  H01L2924/0002

Abstract: An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.

公开(公告)号：US20230205966A1

公开(公告)日：2023-06-29

申请号：US18173731

申请日：2023-02-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuang-Hung CHANG ,  Yuan-Te HOU ,  Chung-Hsing WANG ,  Yung-Chin HOU

IPC: G06F30/392 ,  G06F30/20 ,  G06F30/327 ,  H01L23/528 ,  H01L27/088 ,  G06F30/394

CPC classification number: G06F30/392 ,  G06F30/20 ,  G06F30/327 ,  H01L23/528 ,  H01L27/0886 ,  G06F30/394

Abstract: An IC structure includes first, second, third, and fourth transistors on a substrate, a first net and a second net. The first net includes a plurality of first metal lines routed on a first metallization layer, and a plurality of first metal vias electrically connecting the plurality of first metal lines to the first and second transistors. The second net includes a plurality of second metal lines routed on a second metallization layer, and a plurality of second metal vias electrically connecting the plurality of second metal lines to the third and fourth transistors. A count of the first metal vias of the first net is less than a count of the second metal vias of the second net, and a line height of the first metal line of the first net is greater than a line height of the second metal line of the second net.

公开(公告)号：US20200272777A1

公开(公告)日：2020-08-27

申请号：US16871841

申请日：2020-05-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Lin CHUANG ,  Ching-Fang CHEN ,  Wei-Li CHEN ,  Wei-Pin CHANGCHIEN ,  Yung-Chin HOU ,  Yun-Han LEE

IPC: G06F30/27 ,  G06N20/00 ,  G06F30/30 ,  G06F30/3308 ,  G06F30/337 ,  G06F30/373

Abstract: Electronic design automation (EDA) of the present disclosure, in various embodiments, optimizes designing, simulating, analyzing, and verifying of one or more electronic architectural designs for an electronic device. The EDA of the present disclosure identifies one or more electronic architectural features from the one or more electronic architectural designs. In some situations, the EDA of the present disclosure can manipulate one or more electronic architectural models over multiple iterations using a machine learning process until one or more electronic architectural models from among the one or more electronic architectural models satisfy one or more electronic design targets. The EDA of the present disclosure substitutes the one or more electronic architectural models that satisfy the one or more electronic design targets for the one or more electronic architectural features in the one or more electronic architectural designs to optimize the one or more electronic architectural designs. The EDA of the present disclosure can substitute the one or more electronic architectural models before, during, and/or after designing, simulating, analyzing, and/or verifying of the one or more electronic architectural designs to effectively decrease the time to market (TTM) for the electronic device.

公开(公告)号：US20170161420A1

公开(公告)日：2017-06-08

申请号：US14963151

申请日：2015-12-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yung-Chin HOU ,  Sandeep Kumar GOEL ,  Yun-Han LEE

IPC: G06F17/50 ,  H01L21/768 ,  H01L23/528 ,  H01L25/065 ,  H01L21/48 ,  H01L23/522 ,  H01L23/498 ,  H01L25/00

CPC classification number: G06F17/5072 ,  G06F17/5077 ,  H01L21/486 ,  H01L21/76883 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/528 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06541 ,  H01L2225/06548

Abstract: A partition method includes sorting the plurality of components into a plurality of partitions according to a set of partition criteria and sorting the plurality of components of each partition into a first stack and a second stack according to a set of stack criteria, and the first stack includes a plurality of higher pitch metal layers and the second stack includes a plurality of lower pitch metal layers. The partition criteria include size, power and speed of the component, and the stack criteria include a pitch of a metal layer.