公开(公告)号：US12286706B2

公开(公告)日：2025-04-29

申请号：US17187410

申请日：2021-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Yi Shen ,  Hsin-Lin Wu ,  Yao-Fong Dai ,  Pei-Yuan Tai ,  Chin-Wei Chen ,  Yin-Tun Chou ,  Yuan-Hsin Chi ,  Sheng-Yuan Lin

IPC: C23C14/56 ,  C23C14/50 ,  C23C16/455 ,  H01L21/687

Abstract: The present disclosure relates to exclusion rings for use in processing a semiconductor substrate in a processing chamber, such as a chemical vapor deposition chamber. The exclusion ring includes an alignment structure that cooperates with an alignment structure on a platen on which the exclusion ring will rest during processing of the wafer. The first alignment structure includes a guiding surface which promotes the reception of and positioning of the second alignment structure within the first alignment structure. Methods of utilizing the described exclusion rings are also described.

公开(公告)号：US09633860B2

公开(公告)日：2017-04-25

申请号：US14795751

申请日：2015-07-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chen-Liang Liao ,  Chia-Yao Liang ,  Jui-Long Chen ,  Sheng-Yuan Lin ,  Yi-Lii Huang ,  Kuo-Hsi Lee ,  Po-An Chen

IPC: H01L29/06 ,  H01L21/283 ,  H01L21/3205 ,  H01L21/3213 ,  H01L29/423

CPC classification number: H01L21/76834 ,  H01L21/283 ,  H01L21/28518 ,  H01L21/32053 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/42364 ,  H01L29/4933

Abstract: A semiconductor structure includes an isolation structure, a gate stack, a spacer and a patterned resist protective oxide. The isolation structure is formed in a semiconductor substrate, and electrically isolates device regions of the semiconductor substrate. The gate stack is located on the isolation structure. The spacer is formed along a sidewall of the gate stack on the isolation structure. The patterned resist protective oxide is located on the isolation structure and covers a sidewall of the spacer such that the spacer is interposed between the patterned resist protective oxide and the gate stack.

公开(公告)号：US10083860B2

公开(公告)日：2018-09-25

申请号：US15495901

申请日：2017-04-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chen-Liang Liao ,  Chia-Yao Liang ,  Jui-Long Chen ,  Sheng-Yuan Lin ,  Yi-Lii Huang ,  Kuo-Hsi Lee ,  Po-An Chen

IPC: H01L29/06 ,  H01L21/768 ,  H01L21/3205 ,  H01L21/3213 ,  H01L29/49

CPC classification number: H01L21/76834 ,  H01L21/283 ,  H01L21/28518 ,  H01L21/32053 ,  H01L21/32134 ,  H01L21/32135 ,  H01L21/32139 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/42364 ,  H01L29/4933

Abstract: A method of forming a semiconductor structure includes; (i) forming an isolation structure in a semiconductor substrate, the isolation structure electrically isolating device regions of the semiconductor substrate; (ii) forming a gate structure extending from one of the device regions to the isolation structure; (iii) forming a resist protective oxide layer overlaying the gate structure and the isolation structure; and (iv) patterning the resist protective oxide layer to form a patterned resist protective oxide that covers at least a portion of the isolation structure and a portion of the gate structure on the isolation structure.