公开(公告)号：US20220336665A1

公开(公告)日：2022-10-20

申请号：US17850036

申请日：2022-06-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Chiang Chen ,  Wei-Yang Lee ,  Chia-Pin Lin ,  Yuan-Ching Peng

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/08

Abstract: A device a includes a substrate, two source/drain (S/D) features over the substrate, and semiconductor layers suspended over the substrate and connecting the two S/D features. The device further includes a dielectric layer disposed between two adjacent layers of the semiconductor layers and an air gap between the dielectric layer and one of the S/D features, where a ratio between a length of the air gap to a thickness of the first dielectric layer is in a range of 0.1 to 1.0.

公开(公告)号：US20200075342A1

公开(公告)日：2020-03-05

申请号：US16118684

申请日：2018-08-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Chiang Chen ,  Chun-Hung Lee ,  Ryan Chia-jen Chen ,  Hung-Wei Lin ,  Lung-Kai Mao

IPC: H01L21/3105 ,  H01L21/311 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/762 ,  H01L27/088 ,  H01L29/06

Abstract: Generally, this disclosure provides examples relating to tuning etch rates of dielectric material. In an embodiment, a dielectric material is conformally deposited in first and second trenches in a substrate. Merged lateral growth fronts of the first dielectric material in the first trench form a seam in the first trench. The dielectric material is treated. The treating causes a species to be on first and second upper surfaces of the dielectric material in the first and second trenches, respectively, to be in the seam, and to diffuse into the respective dielectric material in the first and second trenches. After the treating, the respective dielectric material is etched. A ratio of an etch rate of the dielectric material in the second trench to an etch rate of the dielectric material in the first trench is altered by presence of the species in the dielectric material during the etching.

公开(公告)号：US11374128B2

公开(公告)日：2022-06-28

申请号：US16945394

申请日：2020-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Chiang Chen ,  Wei-Yang Lee ,  Chia-Pin Lin ,  Yuan-Ching Peng

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/08 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/775 ,  B82Y10/00

Abstract: A method includes providing a structure having a substrate and a fin. The fin has first and second layers of first and second different semiconductor materials. The first layers and the second layers are alternately stacked over the substrate. The structure further has a sacrificial gate stack engaging a channel region of the fin and gate spacers on sidewalls of the sacrificial gate stack. The method further includes etching a source/drain (S/D) region of the fin, resulting in an S/D trench; partially recessing the second layers exposed in the S/D trench, resulting in a gap between two adjacent layers of the first layers; and depositing a dielectric layer over surfaces of the gate spacers, the first layers, and the second layers. The dielectric layer partially fills the gap, leaving a void sandwiched between the dielectric layer on the two adjacent layers of the first layers.

公开(公告)号：US20210273103A1

公开(公告)日：2021-09-02

申请号：US16945394

申请日：2020-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Chiang Chen ,  Wei-Yang Lee ,  Chia-Pin Lin ,  Yuan-Ching Peng

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/08 ,  H01L27/088

Abstract: A method includes providing a structure having a substrate and a fin. The fin has first and second layers of first and second different semiconductor materials. The first layers and the second layers are alternately stacked over the substrate. The structure further has a sacrificial gate stack engaging a channel region of the fin and gate spacers on sidewalls of the sacrificial gate stack. The method further includes etching a source/drain (S/D) region of the fin, resulting in an S/D trench; partially recessing the second layers exposed in the S/D trench, resulting in a gap between two adjacent layers of the first layers; and depositing a dielectric layer over surfaces of the gate spacers, the first layers, and the second layers. The dielectric layer partially fills the gap, leaving a void sandwiched between the dielectric layer on the two adjacent layers of the first layers.

公开(公告)号：US20240128376A1

公开(公告)日：2024-04-18

申请号：US18395892

申请日：2023-12-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Chiang Chen ,  Wei-Yang Lee ,  Chia-Pin Lin ,  Yuan-Ching Peng

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/08 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/7851 ,  H01L21/823418 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/4991 ,  H01L29/66795 ,  H01L29/78696

Abstract: A device a includes a substrate, two source/drain (S/D) features over the substrate, and semiconductor layers suspended over the substrate and connecting the two S/D features. The device further includes a dielectric layer disposed between two adjacent layers of the semiconductor layers and an air gap between the dielectric layer and one of the S/D features, where a ratio between a length of the air gap to a thickness of the first dielectric layer is in a range of 0.1 to 1.0.

公开(公告)号：US11855220B2

公开(公告)日：2023-12-26

申请号：US17850036

申请日：2022-06-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Chiang Chen ,  Wei-Yang Lee ,  Chia-Pin Lin ,  Yuan-Ching Peng

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08

CPC classification number: H01L29/7851 ,  H01L21/823418 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/66795

Abstract: A device a includes a substrate, two source/drain (S/D) features over the substrate, and semiconductor layers suspended over the substrate and connecting the two S/D features. The device further includes a dielectric layer disposed between two adjacent layers of the semiconductor layers and an air gap between the dielectric layer and one of the S/D features, where a ratio between a length of the air gap to a thickness of the first dielectric layer is in a range of 0.1 to 1.0.

公开(公告)号：US11120997B2

公开(公告)日：2021-09-14

申请号：US16118684

申请日：2018-08-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Chiang Chen ,  Chun-Hung Lee ,  Ryan Chia-jen Chen ,  Hung-Wei Lin ,  Lung-Kai Mao

IPC: H01L21/3105 ,  H01L21/311 ,  H01L29/66 ,  H01L29/06 ,  H01L21/02 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088

Abstract: Generally, this disclosure provides examples relating to tuning etch rates of dielectric material. In an embodiment, a dielectric material is conformally deposited in first and second trenches in a substrate. Merged lateral growth fronts of the first dielectric material in the first trench form a seam in the first trench. The dielectric material is treated. The treating causes a species to be on first and second upper surfaces of the dielectric material in the first and second trenches, respectively, to be in the seam, and to diffuse into the respective dielectric material in the first and second trenches. After the treating, the respective dielectric material is etched. A ratio of an etch rate of the dielectric material in the second trench to an etch rate of the dielectric material in the first trench is altered by presence of the species in the dielectric material during the etching.