公开(公告)号：US20230317674A1

公开(公告)日：2023-10-05

申请号：US18151160

申请日：2023-01-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che Chi SHIH ,  Cheng-Ting CHUNG ,  Han-Yu LIN ,  Wei-Yen WOON ,  Szuya LIAO

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/373 ,  H01L23/528

CPC classification number: H01L24/73 ,  H01L23/5226 ,  H01L23/3735 ,  H01L23/5283 ,  H01L2224/73251

Abstract: Semiconductor devices and methods are provided which facilitate improved thermal conductivity using a high-kappa dielectric bonding layer. In at least one example, a device is provided that includes a first substrate. A semiconductor device layer is disposed on the first substrate, and the semiconductor device layer includes one or more semiconductor devices. Frontside interconnect structure are disposed on the semiconductor device layer, and a bonding layer is disposed on the frontside interconnect structure. A second substrate is disposed on the bonding layer. The bonding layer has a thermal conductivity greater than 10 W/m·K.

公开(公告)号：US20230178435A1

公开(公告)日：2023-06-08

申请号：US17861052

申请日：2022-07-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jui-Chien HUANG ,  Szuya LIAO ,  Cheng-Yin WANG ,  Shih Hao WANG

IPC: H01L21/822 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L29/775 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L21/8221 ,  H01L27/0922 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/78696 ,  H01L29/775 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66439

Abstract: A method includes forming a first transistor of a first semiconductor device. The first semiconductor device includes a first channel region and a gate electrode on the first channel region. A second semiconductor device is bonded to the first semiconductor device by a bonding layer disposed between the first and second semiconductor devices. A second transistor of the second semiconductor device is formed that includes a second channel region and a second gate electrode on the second channel region. The bonding layer is disposed between the first gate electrode of the first transistor and the second gate electrode of the second transistor.

公开(公告)号：US20230307456A1

公开(公告)日：2023-09-28

申请号：US17888261

申请日：2022-08-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Yu LIN ,  Yi-Han WANG ,  Chun-Fu CHENG ,  Cheng-Yin WANG ,  Yi-Bo LIAO ,  Szuya LIAO

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/08 ,  H01L29/786 ,  H01L29/775 ,  H01L29/66 ,  H01L21/8238

CPC classification number: H01L27/0924 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/0847 ,  H01L29/78696 ,  H01L29/775 ,  H01L29/66439 ,  H01L21/823807 ,  H01L21/823814

Abstract: An integrated circuit includes a complimentary field effect transistor (CFET). The CFET includes a first transistor having a first semiconductor nanostructure corresponding to a channel region of the first semiconductor nanostructure and a first gate metal surrounding the second semiconductor nanostructure. The CFET includes a transistor including a second semiconductor nanostructure above the first semiconductor nanostructure and a second gate metal surrounding the second semiconductor nanostructure. The CFET includes an isolation structure between the first and second semiconductor nanostructures.