公开(公告)号：US20220336613A1

公开(公告)日：2022-10-20

申请号：US17564125

申请日：2021-12-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Ju LEE ,  Zhi-Chang LIN ,  Chun-Fu CHENG ,  Chung-Wei WU ,  Zhiqiang WU

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L21/8234

Abstract: A device includes a substrate, a first semiconductor channel over the substrate, and a second semiconductor channel over the substrate and laterally separated from the first semiconductor channel. A gate structure covers and wraps around the first semiconductor channel and the second semiconductor channel. A first source/drain region abuts the first semiconductor channel on a first side of the gate structure, and a second source/drain region abuts the second semiconductor channel on the first side of the gate structure. An isolation structure is under and between the first source/drain region and the second source/drain region, and includes a first isolation region in contact with bottom surfaces of the first and second source/drain regions, and a second isolation region in contact with sidewalls of the first and second source/drain regions, and extending from a bottom surface of the first isolation region to upper surfaces of the first and second source/drain regions.

公开(公告)号：US20220181202A1

公开(公告)日：2022-06-09

申请号：US17682234

申请日：2022-02-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Yu LIN ,  Chun-Fu CHENG ,  Chung-Wei WU ,  Zhiqiang WU

IPC: H01L21/768 ,  H01L21/02

Abstract: The present disclosure describes a method of fabricating a semiconductor structure that includes forming a dummy gate structure over a substrate, forming a first spacer on a sidewall of the dummy gate structure and a second spacer on the first spacer, forming a source/drain structure on the substrate, removing the second spacer, forming a dielectric structure over the source/drain structure, replacing the dummy gate structure with a metal gate structure and a capping structure on the metal gate structure, and forming an opening in the dielectric structure. The opening exposes the source/drain structure. The method further includes forming a dummy spacer on a sidewall of the opening, forming a contact structure in the opening, and removing the dummy spacer to form an air gap between the contact structure and the metal gate structure. The contact structure is in contact with the source/drain structure in the opening.

公开(公告)号：US20210126135A1

公开(公告)日：2021-04-29

申请号：US16667615

申请日：2019-10-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Ju LEE ,  Chun-Fu CHENG ,  Chung-Wei WU ,  Zhiqiang WU

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/423 ,  H01L29/417 ,  H01L29/10 ,  H01L29/06

Abstract: A semiconductor device includes a substrate, a plurality of nanowires, a gate structure, a source/drain epitaxy structure, and a semiconductor layer. The substrate has a protrusion portion. The nanowires extend in a first direction above the protrusion portion of the substrate, the nanowires being arranged in a second direction substantially perpendicular to the first direction. The gate structure wraps around each of the nanowires. The source/drain epitaxy structure is in contact with an end surface of each of the nanowires, in which a bottom surface of the source/drain epitaxy structure is lower than a top surface of the protrusion portion of the substrate. The semiconductor layer is in contact with the bottom surface of the epitaxy structure, in which the semiconductor layer is spaced from the protrusion portion of the substrate.

公开(公告)号：US20210125858A1

公开(公告)日：2021-04-29

申请号：US16823943

申请日：2020-03-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Meng-Yu LIN ,  Chun-Fu CHENG ,  Chung-Wei WU ,  Zhiqiang WU

IPC: H01L21/768 ,  H01L21/02

Abstract: The present disclosure describes a method of fabricating a semiconductor structure that includes forming a dummy gate structure over a substrate, forming a first spacer on a sidewall of the dummy gate structure and a second spacer on the first spacer, forming a source/drain structure on the substrate, removing the second spacer, forming a dielectric structure over the source/drain structure, replacing the dummy gate structure with a metal gate structure and a capping structure on the metal gate structure, and forming an opening in the dielectric structure. The opening exposes the source/drain structure. The method further includes forming a dummy spacer on a sidewall of the opening, forming a contact structure in the opening, and removing the dummy spacer to form an air gap between the contact structure and the metal gate structure. The contact structure is in contact with the source/drain structure in the opening.

公开(公告)号：US20240379803A1

公开(公告)日：2024-11-14

申请号：US18784535

申请日：2024-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Ju LEE ,  Zhi-Chang LIN ,  Chun-Fu CHENG ,  Chung-Wei WU ,  Zhiqiang WU

IPC: H01L29/423 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/786

Abstract: A device includes a substrate, a first semiconductor channel over the substrate, and a second semiconductor channel over the substrate and laterally separated from the first semiconductor channel. A gate structure covers and wraps around the first semiconductor channel and the second semiconductor channel. A first source/drain region abuts the first semiconductor channel on a first side of the gate structure, and a second source/drain region abuts the second semiconductor channel on the first side of the gate structure. An isolation structure is under and between the first source/drain region and the second source/drain region, and includes a first isolation region in contact with bottom surfaces of the first and second source/drain regions, and a second isolation region in contact with sidewalls of the first and second source/drain regions, and extending from a bottom surface of the first isolation region to upper surfaces of the first and second source/drain regions.

公开(公告)号：US20190131274A1

公开(公告)日：2019-05-02

申请号：US15794286

申请日：2017-10-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Zhi-Qiang WU ,  Chun-Fu CHENG ,  Chung-Cheng WU ,  Yi-Han WANG ,  Chia-Wen LIU

IPC: H01L25/065 ,  H01L25/04 ,  H01L21/02

Abstract: A device includes a substrate, a stacked structure and a first gate stack. The stacked structure includes a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked over the substrate. One of the first semiconductor layers has a height greater than a height of one the second semiconductor layers. The first gate stack wraps around the stacked structure.

公开(公告)号：US20180151729A1

公开(公告)日：2018-05-31

申请号：US15471318

申请日：2017-03-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kam-Tou SIO ,  Jiann-Tyng TZENG ,  Charles Chew-Yuen YOUNG ,  Yi-Ming SHEU ,  Chun-Fu CHENG ,  Yi-Han WANG

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/423 ,  H01L21/762 ,  H01L21/02 ,  H01L21/306

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a dielectric layer. The semiconductor device structure also includes a gate stack structure in the dielectric layer. The semiconductor device structure further includes a semiconductor wire partially surrounded by the gate stack structure. In addition, the semiconductor device structure includes a contact electrode in the dielectric layer and electrically connected to the semiconductor wire. The contact electrode and the gate stack structure extend from the semiconductor wire in opposite directions.

公开(公告)号：US20230307456A1

公开(公告)日：2023-09-28

申请号：US17888261

申请日：2022-08-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Yu LIN ,  Yi-Han WANG ,  Chun-Fu CHENG ,  Cheng-Yin WANG ,  Yi-Bo LIAO ,  Szuya LIAO

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/08 ,  H01L29/786 ,  H01L29/775 ,  H01L29/66 ,  H01L21/8238

CPC classification number: H01L27/0924 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/0847 ,  H01L29/78696 ,  H01L29/775 ,  H01L29/66439 ,  H01L21/823807 ,  H01L21/823814

Abstract: An integrated circuit includes a complimentary field effect transistor (CFET). The CFET includes a first transistor having a first semiconductor nanostructure corresponding to a channel region of the first semiconductor nanostructure and a first gate metal surrounding the second semiconductor nanostructure. The CFET includes a transistor including a second semiconductor nanostructure above the first semiconductor nanostructure and a second gate metal surrounding the second semiconductor nanostructure. The CFET includes an isolation structure between the first and second semiconductor nanostructures.

公开(公告)号：US20200294973A1

公开(公告)日：2020-09-17

申请号：US16889498

申请日：2020-06-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Zhi-Qiang WU ,  Chun-Fu CHENG ,  Chung-Cheng WU ,  Yi-Han WANG ,  Chia-Wen LIU

IPC: H01L25/065 ,  H01L21/02 ,  H01L25/04 ,  H01L29/423 ,  H01L29/10 ,  H01L29/08 ,  H01L29/775 ,  H01L29/66 ,  H01L29/786 ,  H01L29/06 ,  H01L27/06 ,  H01L29/40 ,  H01L27/092 ,  H01L29/78 ,  H01L21/8238

Abstract: A method includes forming a stacked structure of a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked in a first direction over a substrate, the first semiconductor layers being thicker than the second semiconductor layers. The method also includes patterning the stacked structure into a first fin structure and a second fin structure extending along a second direction substantially perpendicular to the first direction. The method further includes removing the first semiconductor layers of the first fin structure to form a plurality of nanowires. Each of the nanowires has a first height, there is a distance between two adjacent nanowires along the vertical direction, and the distance is greater than the first height. The method includes forming a first gate structure between the second semiconductor layers of the first fin structure.

公开(公告)号：US20230030571A1

公开(公告)日：2023-02-02

申请号：US17962327

申请日：2022-10-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Ju LEE ,  Chun-Fu CHENG ,  Chung-Wei WU ,  Zhiqiang WU

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/06 ,  H01L29/417 ,  H01L29/10 ,  H01L29/423

Abstract: A method includes forming a plurality of first semiconductor layers and a plurality of second semiconductor layers in an alternate manner over a substrate; patterning the first and second semiconductor layers and the substrate to form a fin structure, in which the fin structure includes a base portion protruding from the substrate and remaining portions of the first and second semiconductor layers; etching the fin structure to form a first recess extending through the remaining portions of the first and second semiconductor layers and into the base portion; epitaxially growing a first epitaxy layer in the first recess; epitaxially growing a second epitaxy layer over the first epitaxy layer; oxidizing the first epitaxy layer, wherein the second epitaxy layer remains unoxidized after the first epitaxy layer is oxidized; and after oxidizing the first epitaxy layer, forming a source/drain epitaxy structure on the second epitaxy layer.