公开(公告)号：US20210327742A1

公开(公告)日：2021-10-21

申请号：US17360157

申请日：2021-06-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Huei Chiu ,  Tsung Fan Yin ,  Chen-Yi Liu ,  Hua-Li Hung ,  Xi-Zong Chen ,  Yi-Wei Chiu

IPC: H01L21/683 ,  H01L21/67 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/687 ,  H01L21/768 ,  H01L29/78

Abstract: Etch uniformity is improved by providing a thermal pad between an insert ring and electrostatic chuck in an etching chamber. The thermal pad provides a continuous passive heat path to dissipate heat from the insert ring and wafer edge to the electrostatic chuck. The thermal pad helps to keep the temperature of the various components in contact with or near the wafer at a more consistent temperature. Because temperature may affect etch rate, such as with etching hard masks over dummy gate formations, a more consistent etch rate is attained. The thermal pad also provides for etch rate uniformity across the whole wafer and not just at the edge. The thermal pad may be used in an etch process to perform gate replacement by removing hard mask layer(s) over a dummy gate electrode.

公开(公告)号：US20220367664A1

公开(公告)日：2022-11-17

申请号：US17814175

申请日：2022-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Chun Chen ,  Tsung Fan Yin ,  Li-Te Hsu ,  Ying Ting Hsia ,  Yi-Wei Chiu

IPC: H01L29/49 ,  H01L29/66 ,  H01L21/28 ,  H01L29/78

Abstract: A method of forming a gate structure includes forming an opening through an insulating layer and forming a first work function metal layer in the opening. The method also includes recessing the first work function metal layer into the opening to form a recessed first work function metal layer, and forming a second work function metal layer in the opening and over the first work function metal layer. The second work function metal layer lines and overhangs the recessed first work function metal layer.

公开(公告)号：US12015070B2

公开(公告)日：2024-06-18

申请号：US17814175

申请日：2022-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Chun Chen ,  Tsung Fan Yin ,  Li-Te Hsu ,  Ying Ting Hsia ,  Yi-Wei Chiu

IPC: H01L21/00 ,  H01L21/28 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming a gate structure includes forming an opening through an insulating layer and forming a first work function metal layer in the opening. The method also includes recessing the first work function metal layer into the opening to form a recessed first work function metal layer, and forming a second work function metal layer in the opening and over the first work function metal layer. The second work function metal layer lines and overhangs the recessed first work function metal layer.

公开(公告)号：US20230387112A1

公开(公告)日：2023-11-30

申请号：US18359492

申请日：2023-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jen-Chih Hsueh ,  Chih-Chang Hung ,  Tsung Fan Yin ,  Yi-Wei Chiu

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/02

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L29/66545 ,  H01L21/32135 ,  H01L21/31116 ,  H01L21/0217 ,  H01L21/823481 ,  H01L29/66492

Abstract: A method includes forming a first semiconductor fin and a second semiconductor fin in a substrate, the first semiconductor fin adjacent the second semiconductor fin, forming a dummy gate structure extending over the first semiconductor fin and the second semiconductor fin, depositing a first dielectric material surrounding the dummy gate structure, replacing the dummy gate structure with a first metal gate structure, performing an etching process on the first metal gate structure and on the first dielectric material to form a first recess in the first metal gate structure and a second recess in the first dielectric material, wherein the first recess extends into the substrate, and wherein the second recess is disposed between the first semiconductor fin and the second semiconductor fin, and depositing a second dielectric material within the first recess.

公开(公告)号：US20220359505A1

公开(公告)日：2022-11-10

申请号：US17869487

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jen-Chih Hsueh ,  Chih-Chang Hung ,  Tsung Fan Yin ,  Yi-Wei Chiu

IPC: H01L27/088 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/8234 ,  H01L29/66

Abstract: A method includes forming a first semiconductor fin and a second semiconductor fin in a substrate, the first semiconductor fin adjacent the second semiconductor fin, forming a dummy gate structure extending over the first semiconductor fin and the second semiconductor fin, depositing a first dielectric material surrounding the dummy gate structure, replacing the dummy gate structure with a first metal gate structure, performing an etching process on the first metal gate structure and on the first dielectric material to form a first recess in the first metal gate structure and a second recess in the first dielectric material, wherein the first recess extends into the substrate, and wherein the second recess is disposed between the first semiconductor fin and the second semiconductor fin, and depositing a second dielectric material within the first recess.

公开(公告)号：US20240371870A1

公开(公告)日：2024-11-07

申请号：US18775497

申请日：2024-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jen-Chih Hsueh ,  Chih-Chang Hung ,  Tsung Fan Yin ,  Yi-Wei Chiu

IPC: H01L27/088 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/8234 ,  H01L29/66

Abstract: A method includes forming a first semiconductor fin and a second semiconductor fin in a substrate, the first semiconductor fin adjacent the second semiconductor fin, forming a dummy gate structure extending over the first semiconductor fin and the second semiconductor fin, depositing a first dielectric material surrounding the dummy gate structure, replacing the dummy gate structure with a first metal gate structure, performing an etching process on the first metal gate structure and on the first dielectric material to form a first recess in the first metal gate structure and a second recess in the first dielectric material, wherein the first recess extends into the substrate, and wherein the second recess is disposed between the first semiconductor fin and the second semiconductor fin, and depositing a second dielectric material within the first recess.

公开(公告)号：US12094877B2

公开(公告)日：2024-09-17

申请号：US18359492

申请日：2023-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jen-Chih Hsueh ,  Chih-Chang Hung ,  Tsung Fan Yin ,  Yi-Wei Chiu

IPC: H01L27/088 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/0217 ,  H01L21/31116 ,  H01L21/32135 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/66545 ,  H01L29/66492

Abstract: A method includes forming a first semiconductor fin and a second semiconductor fin in a substrate, the first semiconductor fin adjacent the second semiconductor fin, forming a dummy gate structure extending over the first semiconductor fin and the second semiconductor fin, depositing a first dielectric material surrounding the dummy gate structure, replacing the dummy gate structure with a first metal gate structure, performing an etching process on the first metal gate structure and on the first dielectric material to form a first recess in the first metal gate structure and a second recess in the first dielectric material, wherein the first recess extends into the substrate, and wherein the second recess is disposed between the first semiconductor fin and the second semiconductor fin, and depositing a second dielectric material within the first recess.

公开(公告)号：US11804488B2

公开(公告)日：2023-10-31

申请号：US17869487

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jen-Chih Hsueh ,  Chih-Chang Hung ,  Tsung Fan Yin ,  Yi-Wei Chiu

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/02

CPC classification number: H01L27/0886 ,  H01L21/0217 ,  H01L21/31116 ,  H01L21/32135 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/66545 ,  H01L29/66492

Abstract: A method includes forming a first semiconductor fin and a second semiconductor fin in a substrate, the first semiconductor fin adjacent the second semiconductor fin, forming a dummy gate structure extending over the first semiconductor fin and the second semiconductor fin, depositing a first dielectric material surrounding the dummy gate structure, replacing the dummy gate structure with a first metal gate structure, performing an etching process on the first metal gate structure and on the first dielectric material to form a first recess in the first metal gate structure and a second recess in the first dielectric material, wherein the first recess extends into the substrate, and wherein the second recess is disposed between the first semiconductor fin and the second semiconductor fin, and depositing a second dielectric material within the first recess.