公开(公告)号：US20210098264A1

公开(公告)日：2021-04-01

申请号：US17121338

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Hua Huang ,  Tzu-Hui Wei ,  Cherng-Shiaw Tsai

IPC: H01L21/311 ,  H01L21/02 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L21/033 ,  H01L23/532

Abstract: An example embodiment of the present disclosure involves a method for semiconductor device fabrication. The method comprises providing a structure that includes a conductive component and an interlayer dielectric (ILD) that includes silicon and surrounds the conductive component, and forming, over the conductive component and the ILD, an etch stop layer (ESL) that includes metal oxide. The ESL includes a first portion in contact with the conductive component and a second portion in contact with the ILD. The method further comprises baking the ESL to transform the metal oxide located in the second portion of the ESL into metal silicon oxide, and selectively etching the ESL so as to remove the first portion of the ESL but not the second portion of the ESL.

公开(公告)号：US12211700B2

公开(公告)日：2025-01-28

申请号：US18324662

申请日：2023-05-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Hua Huang ,  Tzu-Hui Wei ,  Cherng-Shiaw Tsai

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/033 ,  H01L21/311 ,  H01L21/321 ,  H01L21/8234 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: An example embodiment of the present disclosure involves a method for semiconductor device fabrication. The method comprises providing a structure that includes a conductive component and an interlayer dielectric (ILD) that includes silicon and surrounds the conductive component, and forming, over the conductive component and the ILD, an etch stop layer (ESL) that includes metal oxide. The ESL includes a first portion in contact with the conductive component and a second portion in contact with the ILD. The method further comprises baking the ESL to transform the metal oxide located in the second portion of the ESL into metal silicon oxide, and selectively etching the ESL so as to remove the first portion of the ESL but not the second portion of the ESL.

公开(公告)号：US11664237B2

公开(公告)日：2023-05-30

申请号：US17121338

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Hua Huang ,  Tzu-Hui Wei ,  Cherng-Shiaw Tsai

IPC: H01L21/311 ,  H01L21/02 ,  H01L21/033 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/8234 ,  H01L21/321

CPC classification number: H01L21/31144 ,  H01L21/02321 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/5226 ,  H01L23/5329 ,  H01L21/02142 ,  H01L21/02145 ,  H01L21/02148 ,  H01L21/02153 ,  H01L21/3212 ,  H01L21/7684 ,  H01L21/823475

Abstract: An example embodiment of the present disclosure involves a method for semiconductor device fabrication. The method comprises providing a structure that includes a conductive component and an interlayer dielectric (ILD) that includes silicon and surrounds the conductive component, and forming, over the conductive component and the ILD, an etch stop layer (ESL) that includes metal oxide. The ESL includes a first portion in contact with the conductive component and a second portion in contact with the ILD. The method further comprises baking the ESL to transform the metal oxide located in the second portion of the ESL into metal silicon oxide, and selectively etching the ESL so as to remove the first portion of the ESL but not the second portion of the ESL.

公开(公告)号：US20250167002A1

公开(公告)日：2025-05-22

申请号：US19027220

申请日：2025-01-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Hua Huang ,  Cherng-Shiaw Tsai ,  Tzu-Hui Wei

IPC: H01L21/311 ,  H01L21/02 ,  H01L21/033 ,  H01L21/321 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H10D84/01 ,  H10D84/03

Abstract: An example embodiment of the present disclosure involves a method for semiconductor device fabrication. The method comprises providing a structure that includes a conductive component and an interlayer dielectric (ILD) that includes silicon and surrounds the conductive component, and forming, over the conductive component and the ILD, an etch stop layer (ESL) that includes metal oxide. The ESL includes a first portion in contact with the conductive component and a second portion in contact with the ILD. The method further comprises baking the ESL to transform the metal oxide located in the second portion of the ESL into metal silicon oxide, and selectively etching the ESL so as to remove the first portion of the ESL but not the second portion of the ESL.

公开(公告)号：US20230298900A1

公开(公告)日：2023-09-21

申请号：US18324662

申请日：2023-05-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Hua Huang ,  Tzu-Hui Wei ,  Cherng-Shiaw Tsai

IPC: H01L21/311 ,  H01L21/02 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L21/033 ,  H01L23/532

CPC classification number: H01L21/31144 ,  H01L21/02321 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/5226 ,  H01L21/31116 ,  H01L21/0337 ,  H01L23/5329 ,  H01L21/0332 ,  H01L21/823475

Abstract: An example embodiment of the present disclosure involves a method for semiconductor device fabrication. The method comprises providing a structure that includes a conductive component and an interlayer dielectric (ILD) that includes silicon and surrounds the conductive component, and forming, over the conductive component and the ILD, an etch stop layer (ESL) that includes metal oxide. The ESL includes a first portion in contact with the conductive component and a second portion in contact with the ILD. The method further comprises baking the ESL to transform the metal oxide located in the second portion of the ESL into metal silicon oxide, and selectively etching the ESL so as to remove the first portion of the ESL but not the second portion of the ESL.

公开(公告)号：US20200006083A1

公开(公告)日：2020-01-02

申请号：US16195304

申请日：2018-11-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Hua Huang ,  Tzu-Hui Wei ,  Cherng-Shiaw Tsai

IPC: H01L21/311 ,  H01L21/033 ,  H01L21/02 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532

Abstract: An example embodiment of the present disclosure involves a method for semiconductor device fabrication. The method comprises providing a structure that includes a conductive component and an interlayer dielectric (ILD) that includes silicon and surrounds the conductive component, and forming, over the conductive component and the ILD, an etch stop layer (ESL) that includes metal oxide. The ESL includes a first portion in contact with the conductive component and a second portion in contact with the ILD. The method further comprises baking the ESL to transform the metal oxide located in the second portion of the ESL into metal silicon oxide, and selectively etching the ESL so as to remove the first portion of the ESL but not the second portion of the ESL.

公开(公告)号：US10032640B1

公开(公告)日：2018-07-24

申请号：US15628114

申请日：2017-06-20

Applicant: Taiwan Semiconductor Manufacturing, Co., Ltd.

Inventor： Chien-Hua Huang ,  Chung-Ju Lee ,  Ming-Hui Weng ,  Tzu-Hui Wei

IPC: H01L21/308

Abstract: Methods of fabricating a semiconductor structure using a photoresist cross link process and a photoresist de-cross link process are described. A cross link bottom layer is employed during the fabricating process and the photoresist de-cross link process de-cross links the cross link bottom layer before the bottom layer is removed. The incorporation of the photoresist de-cross link process with the usage of the cross link bottom layer provides a cost effective and low defect level solution to fabricate the semiconductor structure.