公开(公告)号：US20220359735A1

公开(公告)日：2022-11-10

申请号：US17872531

申请日：2022-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Shu Wu ,  Ying-Ya Hsu ,  Ching-Yu Pan ,  Hsiu-Hao Tsao ,  An Chyi Wei ,  Yuan-Hung Chiu

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/02 ,  H01L27/088

Abstract: A method includes forming a fin on a substrate, forming an insulating material over the fin, recessing the insulating material to form an isolation region surrounding the fin, wherein an upper portion of the fin protrudes above the isolation region, performing a trimming process to reduce a width of the upper portion of the fin, and forming a gate structure extending over the isolation region and the upper portion of the fin.

公开(公告)号：US11437498B2

公开(公告)日：2022-09-06

申请号：US17113351

申请日：2020-12-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Shu Wu ,  Ying-Ya Hsu ,  Ching-Yu Pan ,  Hsiu-Hao Tsao ,  An Chyi Wei ,  Yuan-Hung Chiu

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L21/02

Abstract: A method includes forming a fin on a substrate, forming an insulating material over the fin, recessing the insulating material to form an isolation region surrounding the fin, wherein an upper portion of the fin protrudes above the isolation region, performing a trimming process to reduce a width of the upper portion of the fin, and forming a gate structure extending over the isolation region and the upper portion of the fin.

公开(公告)号：US10276449B1

公开(公告)日：2019-04-30

申请号：US15821904

申请日：2017-11-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Shu Wu ,  Ying-Ya Hsu ,  Shu-Uei Jang ,  Yu-Wen Wang ,  Ryan Chia-Jen Chen ,  An-Chyi Wei

IPC: H01L21/76 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/165 ,  H01L21/311

Abstract: A method for forming a semiconductor device structure includes providing a substrate having a first fin structure and a second fin structure that are capped by a patterned hard mask structure. A liner layer and an overlying insulating layer are formed between the first and second fin structures. A multi-step etching process including a first step of selectively removing the patterned hard mask structure and a second step of in-situ and selectively removing a portion of the insulating layer to form an isolation feature is performed. The process gas used in the multi-step etching process includes a first etching gas and a second etching gas. The flow rate of the first etching gas is greater than that of the second etching gas in the first step and the flow rate of the first etching gas is less than that of the second etching gas in the second step.

公开(公告)号：US11735651B2

公开(公告)日：2023-08-22

申请号：US17872531

申请日：2022-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Shu Wu ,  Ying-Ya Hsu ,  Ching-Yu Pan ,  Hsiu-Hao Tsao ,  An Chyi Wei ,  Yuan-Hung Chiu

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/66 ,  H01L21/02 ,  H01L27/088

CPC classification number: H01L29/66818 ,  H01L21/02236 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/7853

Abstract: A method includes forming a fin on a substrate, forming an insulating material over the fin, recessing the insulating material to form an isolation region surrounding the fin, wherein an upper portion of the fin protrudes above the isolation region, performing a trimming process to reduce a width of the upper portion of the fin, and forming a gate structure extending over the isolation region and the upper portion of the fin.

公开(公告)号：US20210111272A1

公开(公告)日：2021-04-15

申请号：US17113351

申请日：2020-12-07

Applicant: Taiwan Semiconductor manufacturing Co., Ltd.

Inventor： Chung-Shu Wu ,  Ying-Ya Hsu ,  Ching-Yu Pan ,  Hsiu-Hao Tsao ,  An Chyi Wei ,  Yuan-Hung Chiu

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/02 ,  H01L27/088

Abstract: A method includes forming a fin on a substrate, forming an insulating material over the fin, recessing the insulating material to form an isolation region surrounding the fin, wherein an upper portion of the fin protrudes above the isolation region, performing a trimming process to reduce a width of the upper portion of the fin, and forming a gate structure extending over the isolation region and the upper portion of the fin.