公开(公告)号：US20220359735A1

公开(公告)日：2022-11-10

申请号：US17872531

申请日：2022-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Shu Wu ,  Ying-Ya Hsu ,  Ching-Yu Pan ,  Hsiu-Hao Tsao ,  An Chyi Wei ,  Yuan-Hung Chiu

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/02 ,  H01L27/088

Abstract: A method includes forming a fin on a substrate, forming an insulating material over the fin, recessing the insulating material to form an isolation region surrounding the fin, wherein an upper portion of the fin protrudes above the isolation region, performing a trimming process to reduce a width of the upper portion of the fin, and forming a gate structure extending over the isolation region and the upper portion of the fin.

公开(公告)号：US11735651B2

公开(公告)日：2023-08-22

申请号：US17872531

申请日：2022-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Shu Wu ,  Ying-Ya Hsu ,  Ching-Yu Pan ,  Hsiu-Hao Tsao ,  An Chyi Wei ,  Yuan-Hung Chiu

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/66 ,  H01L21/02 ,  H01L27/088

CPC classification number: H01L29/66818 ,  H01L21/02236 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/7853

Abstract: A method includes forming a fin on a substrate, forming an insulating material over the fin, recessing the insulating material to form an isolation region surrounding the fin, wherein an upper portion of the fin protrudes above the isolation region, performing a trimming process to reduce a width of the upper portion of the fin, and forming a gate structure extending over the isolation region and the upper portion of the fin.

公开(公告)号：US20210111272A1

公开(公告)日：2021-04-15

申请号：US17113351

申请日：2020-12-07

Applicant: Taiwan Semiconductor manufacturing Co., Ltd.

Inventor： Chung-Shu Wu ,  Ying-Ya Hsu ,  Ching-Yu Pan ,  Hsiu-Hao Tsao ,  An Chyi Wei ,  Yuan-Hung Chiu

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/02 ,  H01L27/088

Abstract: A method includes forming a fin on a substrate, forming an insulating material over the fin, recessing the insulating material to form an isolation region surrounding the fin, wherein an upper portion of the fin protrudes above the isolation region, performing a trimming process to reduce a width of the upper portion of the fin, and forming a gate structure extending over the isolation region and the upper portion of the fin.

公开(公告)号：US11437498B2

公开(公告)日：2022-09-06

申请号：US17113351

申请日：2020-12-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Shu Wu ,  Ying-Ya Hsu ,  Ching-Yu Pan ,  Hsiu-Hao Tsao ,  An Chyi Wei ,  Yuan-Hung Chiu

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L21/02

Abstract: A method includes forming a fin on a substrate, forming an insulating material over the fin, recessing the insulating material to form an isolation region surrounding the fin, wherein an upper portion of the fin protrudes above the isolation region, performing a trimming process to reduce a width of the upper portion of the fin, and forming a gate structure extending over the isolation region and the upper portion of the fin.

公开(公告)号：US10032887B2

公开(公告)日：2018-07-24

申请号：US15488814

申请日：2017-04-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Lien Huang ,  Li-Te Lin ,  Yuan-Hung Chiu ,  Han-Yu Lin

IPC: H01L29/66 ,  H01L21/00 ,  H01L21/02 ,  H01L21/04 ,  H01L21/28 ,  H01L29/08

Abstract: A method includes forming a first gate structure in a dielectric layer over a substrate, wherein the first gate structure includes a first gate stack and spacers along sidewalls of the first gate stack; recessing the first gate stack to form a first trench defined by the spacers, wherein upper portions of the spacers are exposed within the first trench; forming a first capping layer in the first trench, wherein the first capping layer has a first portion disposed along sidewalls of the upper portions of the spacers and a second portion disposed over the recessed first gate stack; applying a first implantation to convert the second portion of the first capping layer into a second capping layer; selectively removing the first portion of the capping layer to expose the upper portions of the spacers; and selectively removing the upper portions of the spacers.

公开(公告)号：US20170365691A1

公开(公告)日：2017-12-21

申请号：US15488814

申请日：2017-04-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Lien Huang ,  Li-Te Lin ,  Yuan-Hung Chiu ,  Han-Yu Lin

IPC: H01L29/66 ,  H01L21/04 ,  H01L21/02 ,  H01L21/28

CPC classification number: H01L29/66583 ,  H01L21/02642 ,  H01L21/0465 ,  H01L21/26586 ,  H01L21/28247 ,  H01L21/31111 ,  H01L21/31155 ,  H01L21/32133 ,  H01L21/76834 ,  H01L21/76897 ,  H01L27/1104 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78 ,  H01L2224/0348 ,  H01L2224/03916

Abstract: A method includes forming a first gate structure in a dielectric layer over a substrate, wherein the first gate structure includes a first gate stack and spacers along sidewalls of the first gate stack; recessing the first gate stack to form a first trench defined by the spacers, wherein upper portions of the spacers are exposed within the first trench; forming a first capping layer in the first trench, wherein the first capping layer has a first portion disposed along sidewalls of the upper portions of the spacers and a second portion disposed over the recessed first gate stack; applying a first implantation to convert the second portion of the first capping layer into a second capping layer; selectively removing the first portion of the capping layer to expose the upper portions of the spacers; and selectively removing the upper portions of the spacers.

公开(公告)号：US09627258B1

公开(公告)日：2017-04-18

申请号：US15183452

申请日：2016-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Lien Huang ,  Li-Te Lin ,  Yuan-Hung Chiu ,  Han-Yu Lin

IPC: H01L21/00 ,  H01L21/768 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/3115 ,  H01L23/522 ,  H01L27/11

CPC classification number: H01L29/66583 ,  H01L21/02642 ,  H01L21/0465 ,  H01L21/26586 ,  H01L21/28247 ,  H01L21/31111 ,  H01L21/31155 ,  H01L21/32133 ,  H01L21/76834 ,  H01L21/76897 ,  H01L27/1104 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78 ,  H01L2224/0348 ,  H01L2224/03916

Abstract: A method includes forming a first gate structure in a dielectric layer over a substrate, wherein the first gate structure includes a first gate stack and spacers along sidewalls of the first gate stack; recessing the first gate stack to form a first trench defined by the spacers, wherein upper portions of the spacers are exposed within the first trench; forming a first capping layer in the first trench, wherein the first capping layer has a first portion disposed along sidewalls of the upper portions of the spacers and a second portion disposed over the recessed first gate stack; applying a first implantation to convert the second portion of the first capping layer into a second capping layer; selectively removing the first portion of the capping layer to expose the upper portions of the spacers; and selectively removing the upper portions of the spacers.