公开(公告)号：US20220359735A1

公开(公告)日：2022-11-10

申请号：US17872531

申请日：2022-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Shu Wu ,  Ying-Ya Hsu ,  Ching-Yu Pan ,  Hsiu-Hao Tsao ,  An Chyi Wei ,  Yuan-Hung Chiu

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/02 ,  H01L27/088

Abstract: A method includes forming a fin on a substrate, forming an insulating material over the fin, recessing the insulating material to form an isolation region surrounding the fin, wherein an upper portion of the fin protrudes above the isolation region, performing a trimming process to reduce a width of the upper portion of the fin, and forming a gate structure extending over the isolation region and the upper portion of the fin.

公开(公告)号：US11437498B2

公开(公告)日：2022-09-06

申请号：US17113351

申请日：2020-12-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Shu Wu ,  Ying-Ya Hsu ,  Ching-Yu Pan ,  Hsiu-Hao Tsao ,  An Chyi Wei ,  Yuan-Hung Chiu

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L21/02

Abstract: A method includes forming a fin on a substrate, forming an insulating material over the fin, recessing the insulating material to form an isolation region surrounding the fin, wherein an upper portion of the fin protrudes above the isolation region, performing a trimming process to reduce a width of the upper portion of the fin, and forming a gate structure extending over the isolation region and the upper portion of the fin.

公开(公告)号：US10672613B2

公开(公告)日：2020-06-02

申请号：US16115394

申请日：2018-08-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shu-Uei Jang ,  Chien-Hua Tseng ,  Chung-Shu Wu ,  Ya-Yi Tsai ,  Ryan Chia-Jen Chen ,  An-Chyi Wei

IPC: H01L21/28 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3213 ,  H01L29/78 ,  H01L21/02 ,  H01L21/762 ,  H01L29/66 ,  H01L29/06

Abstract: A method of forming a semiconductor structure includes forming a metal gate stack over a shallow trench isolation (STI) material in a semiconductor substrate, forming an interlayer dielectric over the STI material, recessing the interlayer dielectric to a height lower than a top surface of the metal gate stack, forming a helmet structure over the recessed interlayer dielectric, and after forming the helmet structure, etching the metal gate stack until reaching the STI material.

公开(公告)号：US10276449B1

公开(公告)日：2019-04-30

申请号：US15821904

申请日：2017-11-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Shu Wu ,  Ying-Ya Hsu ,  Shu-Uei Jang ,  Yu-Wen Wang ,  Ryan Chia-Jen Chen ,  An-Chyi Wei

IPC: H01L21/76 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/165 ,  H01L21/311

Abstract: A method for forming a semiconductor device structure includes providing a substrate having a first fin structure and a second fin structure that are capped by a patterned hard mask structure. A liner layer and an overlying insulating layer are formed between the first and second fin structures. A multi-step etching process including a first step of selectively removing the patterned hard mask structure and a second step of in-situ and selectively removing a portion of the insulating layer to form an isolation feature is performed. The process gas used in the multi-step etching process includes a first etching gas and a second etching gas. The flow rate of the first etching gas is greater than that of the second etching gas in the first step and the flow rate of the first etching gas is less than that of the second etching gas in the second step.

公开(公告)号：US11735651B2

公开(公告)日：2023-08-22

申请号：US17872531

申请日：2022-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Shu Wu ,  Ying-Ya Hsu ,  Ching-Yu Pan ,  Hsiu-Hao Tsao ,  An Chyi Wei ,  Yuan-Hung Chiu

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/66 ,  H01L21/02 ,  H01L27/088

CPC classification number: H01L29/66818 ,  H01L21/02236 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/7853

Abstract: A method includes forming a fin on a substrate, forming an insulating material over the fin, recessing the insulating material to form an isolation region surrounding the fin, wherein an upper portion of the fin protrudes above the isolation region, performing a trimming process to reduce a width of the upper portion of the fin, and forming a gate structure extending over the isolation region and the upper portion of the fin.

公开(公告)号：US11063043B2

公开(公告)日：2021-07-13

申请号：US16712162

申请日：2019-12-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Shu Wu ,  Shu-Uei Jang ,  Wei-Yeh Tang ,  Ryan Chia-Jen Chen ,  An-Chyi Wei

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/311 ,  H01L29/161

Abstract: A method for forming a FinFET device structure is provided. The method includes forming a first fin structure and a second fin structure over a substrate and forming a liner layer over the first fin structure and the second fin structure. The method also includes forming an isolation layer over the liner layer and removing a portion of the liner layer and a portion of the isolation layer, such that the liner layer includes a first liner layer on an outer sidewall surface of the first fin structure and a second liner layer on an inner sidewall surface of the first fin structure, and a top surface of the second liner layer is higher than a top surface of the first liner layer.

公开(公告)号：US20210111272A1

公开(公告)日：2021-04-15

申请号：US17113351

申请日：2020-12-07

Applicant: Taiwan Semiconductor manufacturing Co., Ltd.

Inventor： Chung-Shu Wu ,  Ying-Ya Hsu ,  Ching-Yu Pan ,  Hsiu-Hao Tsao ,  An Chyi Wei ,  Yuan-Hung Chiu

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/02 ,  H01L27/088

Abstract: A method includes forming a fin on a substrate, forming an insulating material over the fin, recessing the insulating material to form an isolation region surrounding the fin, wherein an upper portion of the fin protrudes above the isolation region, performing a trimming process to reduce a width of the upper portion of the fin, and forming a gate structure extending over the isolation region and the upper portion of the fin.

公开(公告)号：US10515952B2

公开(公告)日：2019-12-24

申请号：US15669013

申请日：2017-08-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Shu Wu ,  Shu-Uei Jang ,  Wei-Yeh Tang ,  Ryan Chia-Jen Chen ,  An-Chyi Wei

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/311 ,  H01L29/161

Abstract: A FinFET device structure and method for forming the same are provided. The FinFET device structure includes a first fin structure extending above a substrate, and the first fin structure includes a portion made of silicon germanium (SiGe). The FinFET device structure includes a second fin structure adjacent to the first fin structure. The FinFET device structure also includes a first liner layer formed on the outer sidewall surface of the first fin structure and a second liner layer formed on the inner sidewall surface of the first fin structure. The FinFET device structure further includes a first isolation structure formed on the substrate, and the first liner layer is between the first isolation structure and the first fin structure, and a top surface of the second liner layer is higher than a top surface of the first liner layer.