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公开(公告)号：US20180179047A1
公开(公告)日：2018-06-28
申请号：US15885016
申请日：2018-01-31
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yu-Jui Chen , I-Shi Wang , Ren-Dou Lee , Jen-Hao Liu
CPC classification number: B81B3/0005 , B81B3/001 , B81B2203/04 , B81B2207/012 , B81B2207/07 , B81C1/00984 , B81C2201/0132 , B81C2203/037 , B81C2203/0785
Abstract: The present disclosure relates to a MEMS package with a rough metal anti-stiction layer, to improve stiction characteristics, and an associated method of formation. In some embodiments, the MEMS package includes a MEMS IC bonded to a CMOS IC. The CMOS IC has a CMOS substrate and an interconnect structure disposed over the CMOS substrate. The interconnect structure includes a plurality of metal layers disposed within a plurality of dielectric layers. The MEMS IC is bonded to the CMOS IC, enclosing a cavity between the MEMS IC and the CMOS IC and a moveable mass arranged in the cavity. The MEMS package further includes an anti-stiction layer disposed under the moveable mass. The anti-stiction layer is made of metal and has a rough top surface.
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公开(公告)号：US11192778B2
公开(公告)日：2021-12-07
申请号：US16927223
申请日：2020-07-13
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yu-Jui Chen , I-Shi Wang , Ren-Dou Lee , Jen-Hao Liu
Abstract: A method includes: providing a first substrate on which a plurality of first semiconductor devices is formed; providing a second substrate on which a plurality of second semiconductor devices is formed; and coupling the first and second substrates by contacting respective dummy pads of the first and second substrates, wherein at least one of the dummy pads of the first and second substrates comprises plural peaks and valleys.
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公开(公告)号：US10710872B2
公开(公告)日：2020-07-14
申请号：US15833072
申请日：2017-12-06
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yu-Jui Chen , I-Shi Wang , Ren-Dou Lee , Jen-Hao Liu
Abstract: A method includes: providing a first substrate on which a plurality of first semiconductor devices is formed; providing a second substrate on which a plurality of second semiconductor devices is formed; and coupling the first and second substrates by contacting respective dummy pads of the first and second substrates, wherein at least one of the dummy pads of the first and second substrates comprises plural peaks and valleys.
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公开(公告)号：US10759654B2
公开(公告)日：2020-09-01
申请号：US16229902
申请日：2018-12-21
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yu-Jui Chen , I-Shi Wang , Ren-Dou Lee , Jen-Hao Liu
Abstract: The present disclosure relates to a method for manufacturing a microelectromechanical systems (MEMS) package. The method comprises providing a CMOS IC including CMOS devices arranged within a CMOS substrate. The method further comprises forming and patterning a metal layer over the CMOS substrate to form an anti-stiction layer and a fixed electrode plate and forming a rough top surface for the anti-stiction layer. The method further comprises providing a MEMS IC comprising a moveable mass arranged within a recess of a MEMS substrate and bonding the CMOS IC to the MEMS IC to enclose a cavity between the moveable mass and the fixed electrode plate and the anti-stiction layer.
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公开(公告)号：US20190119099A1
公开(公告)日：2019-04-25
申请号：US16229902
申请日：2018-12-21
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yu-Jui Chen , I-Shi Wang , Ren-Dou Lee , Jen-Hao Liu
CPC classification number: B81B3/0005 , B81B3/001 , B81B2203/04 , B81B2207/012 , B81B2207/07 , B81C1/00984 , B81C2201/0132 , B81C2203/037 , B81C2203/0785
Abstract: The present disclosure relates to a method for manufacturing a microelectromechanical systems (MEMS) package. The method comprises providing a CMOS IC including CMOS devices arranged within a CMOS substrate. The method further comprises forming and patterning a metal layer over the CMOS substrate to form an anti-stiction layer and a fixed electrode plate and forming a rough top surface for the anti-stiction layer. The method further comprises providing a MEMS IC comprising a moveable mass arranged within a recess of a MEMS substrate and bonding the CMOS IC to the MEMS IC to enclose a cavity between the moveable mass and the fixed electrode plate and the anti-stiction layer.
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Patent Agency Ranking
公开(公告)号：US10173886B2
公开(公告)日：2019-01-08
申请号：US15885016
申请日：2018-01-31
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yu-Jui Chen , I-Shi Wang , Ren-Dou Lee , Jen-Hao Liu
Abstract: The present disclosure relates to a MEMS package with a rough metal anti-stiction layer, to improve stiction characteristics, and an associated method of formation. In some embodiments, the MEMS package includes a MEMS IC bonded to a CMOS IC. The CMOS IC has a CMOS substrate and an interconnect structure disposed over the CMOS substrate. The interconnect structure includes a plurality of metal layers disposed within a plurality of dielectric layers. The MEMS IC is bonded to the CMOS IC, enclosing a cavity between the MEMS IC and the CMOS IC and a moveable mass arranged in the cavity. The MEMS package further includes an anti-stiction layer disposed under the moveable mass. The anti-stiction layer is made of metal and has a rough top surface.
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公开(公告)号：US09884755B2
公开(公告)日：2018-02-06
申请号：US15006301
申请日：2016-01-26
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yu-Jui Chen , I-Shi Wang , Ren-Dou Lee , Jen-Hao Liu
CPC classification number: B81B3/0005 , B81B3/001 , B81B2203/04 , B81B2207/012 , B81B2207/07 , B81C1/00984 , B81C2201/0132 , B81C2203/037 , B81C2203/0785
Abstract: The present disclosure relates to a MEMS package with a rough metal anti-stiction layer, to improve stiction characteristics, and an associated method of formation. In some embodiments, the MEMS package includes a MEMS IC bonded to a CMOS IC. The CMOS IC has a CMOS substrate and an interconnect structure disposed over the CMOS substrate. The interconnect structure includes a plurality of metal layers disposed within a plurality of dielectric layers. The MEMS IC is bonded to an upper surface of the interconnect structure and, in cooperation with the CMOS IC, enclosing a cavity between the MEMS IC and the CMOS IC. The MEMS IC has a moveable mass arranged in the cavity. The MEMS package further includes an anti-stiction layer disposed on the upper surface of the interconnect structure under the moveable mass. The anti-stiction layer is made of metal and has a rough top surface.
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公开(公告)号：US20170210612A1
公开(公告)日：2017-07-27
申请号：US15006301
申请日：2016-01-26
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yu-Jui Chen , I-Shi Wang , Ren-Dou Lee , Jen-Hao Liu
CPC classification number: B81B3/0005 , B81B3/001 , B81B2203/04 , B81B2207/012 , B81B2207/07 , B81C1/00984 , B81C2201/0132 , B81C2203/037 , B81C2203/0785
Abstract: The present disclosure relates to a MEMS package with a rough metal anti-stiction layer, to improve stiction characteristics, and an associated method of formation. In some embodiments, the MEMS package includes a MEMS IC bonded to a CMOS IC. The CMOS IC has a CMOS substrate and an interconnect structure disposed over the CMOS substrate. The interconnect structure includes a plurality of metal layers disposed within a plurality of dielectric layers. The MEMS IC is bonded to an upper surface of the interconnect structure and, in cooperation with the CMOS IC, enclosing a cavity between the MEMS IC and the CMOS IC. The MEMS IC has a moveable mass arranged in the cavity. The MEMS package further includes an anti-stiction layer disposed on the upper surface of the interconnect structure under the moveable mass. The anti-stiction layer is made of metal and has a rough top surface.
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公开(公告)号：US09481567B2
公开(公告)日：2016-11-01
申请号：US14302982
申请日：2014-06-12
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： I-Shi Wang , Yu-Jui Chen , Ting-Ying Chien , Jen-Hao Liu , Ren-Dou Lee
CPC classification number: B81B7/0077 , B81B3/0005 , B81C1/00269 , B81C1/00333 , B81C1/00373 , B81C1/0096
Abstract: A micro electro mechanical system (MEMS) structure is provided, which includes a first substrate, a second substrate, a MEMS device and a hydrophobic semiconductor layer. The first substrate has a first portion. The second substrate is substantially parallel to the first substrate and has a second portion substantially aligned with the first portion. The MEMS device is between the first portion and the second portion. The hydrophobic semiconductor layer is made of germanium (Ge), silicon (Si) or a combination thereof on the first portion, the second portion or the first portion and the second portion and faces toward the MEMS device. A cap substrate for a MEMS device and a method of fabricating the same are also provided.
Abstract translation: 提供了一种微电子机械系统（MEMS）结构，其包括第一衬底，第二衬底，MEMS器件和疏水性半导体层。 第一基板具有第一部分。 第二基板基本上平行于第一基板并且具有与第一部分大致对准的第二部分。 MEMS器件在第一部分和第二部分之间。 疏水性半导体层由锗（Ge），硅（Si）或其组合构成在第一部分，第二部分或第一部分和第二部分上并面向MEMS器件。 还提供了用于MEMS器件的盖衬底及其制造方法。
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公开(公告)号：US20150360938A1
公开(公告)日：2015-12-17
申请号：US14302982
申请日：2014-06-12
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： I-Shi Wang , Yu-Jui Chen , Ting-Ying Chien , Jen-Hao Liu , Ren-Dou Lee
CPC classification number: B81B7/0077 , B81B3/0005 , B81C1/00269 , B81C1/00333 , B81C1/00373 , B81C1/0096
Abstract: A micro electro mechanical system (MEMS) structure is provided, which includes a first substrate, a second substrate, a MEMS device and a hydrophobic semiconductor layer. The first substrate has a first portion. The second substrate is substantially parallel to the first substrate and has a second portion substantially aligned with the first portion. The MEMS device is between the first portion and the second portion. The hydrophobic semiconductor layer is made of germanium (Ge), silicon (Si) or a combination thereof on the first portion, the second portion or the first portion and the second portion and faces toward the MEMS device. A cap substrate for a MEMS device and a method of fabricating the same are also provided.
Abstract translation: 提供了一种微电子机械系统（MEMS）结构，其包括第一衬底，第二衬底，MEMS器件和疏水性半导体层。 第一基板具有第一部分。 第二基板基本上平行于第一基板并且具有与第一部分大致对准的第二部分。 MEMS器件在第一部分和第二部分之间。 疏水性半导体层由锗（Ge），硅（Si）或其组合构成在第一部分，第二部分或第一部分和第二部分上并面向MEMS器件。 还提供了用于MEMS器件的盖衬底及其制造方法。
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