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公开(公告)号：US11174156B2
公开(公告)日：2021-11-16
申请号：US16829196
申请日：2020-03-25
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chih-Hang Chang , I-Shi Wang , Jen-Hao Liu
Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first wafer comprising a first face and a second face opposite the first face and having a plurality of predetermined die areas. A plurality of recesses are disposed in the first face of the first wafer. A first recess of the plurality of recesses extends in a direction substantially parallel to a first edge of at least one of the plurality of predetermined die areas and laterally surrounds the at least one of the plurality of predetermined die areas. A second wafer is bonded to the second face of the first wafer.
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公开(公告)号：US11034578B2
公开(公告)日：2021-06-15
申请号：US15930605
申请日：2020-05-13
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chih-Chien Yang , Ming-Lun Shih , Ren-Dou Lee , Jen-Hao Liu
Abstract: A multi-layer sealing film for high seal yield is provided. In some embodiments, a substrate comprises a vent opening extending through the substrate, from an upper side of the substrate to a lower side of the substrate. The upper side of the substrate has a first pressure, and the lower side of the substrate has a second pressure different than the first pressure. The multi-layer sealing film covers and seals the vent opening to prevent the first pressure from equalizing with the second pressure through the vent opening. Further, the multi-layer sealing film comprises a pair of metal layers and a barrier layer sandwiched between metal layers. Also provided is a microelectromechanical systems (MEMS) package comprising the multilayer sealing film, and a method for manufacturing the multi-layer sealing film.
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公开(公告)号：US20200024125A1
公开(公告)日：2020-01-23
申请号：US16386993
申请日：2019-04-17
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chih-Hang Chang , I-Shi Wang , Jen-Hao Liu
IPC: B81B3/00
Abstract: A microelectromechanical systems (MEMS) package with roughness for high quality anti-stiction is provided. A device substrate is arranged over a support device. The device substrate comprises a movable element with a lower surface that is rough and that is arranged within a cavity. A dielectric layer is arranged between the support device and the device substrate. The dielectric layer laterally encloses the cavity. An anti-stiction layer lines the lower surface of the movable element. A method for manufacturing the MEMS package is also provided.
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公开(公告)号：US20180179047A1
公开(公告)日：2018-06-28
申请号：US15885016
申请日：2018-01-31
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yu-Jui Chen , I-Shi Wang , Ren-Dou Lee , Jen-Hao Liu
CPC classification number: B81B3/0005 , B81B3/001 , B81B2203/04 , B81B2207/012 , B81B2207/07 , B81C1/00984 , B81C2201/0132 , B81C2203/037 , B81C2203/0785
Abstract: The present disclosure relates to a MEMS package with a rough metal anti-stiction layer, to improve stiction characteristics, and an associated method of formation. In some embodiments, the MEMS package includes a MEMS IC bonded to a CMOS IC. The CMOS IC has a CMOS substrate and an interconnect structure disposed over the CMOS substrate. The interconnect structure includes a plurality of metal layers disposed within a plurality of dielectric layers. The MEMS IC is bonded to the CMOS IC, enclosing a cavity between the MEMS IC and the CMOS IC and a moveable mass arranged in the cavity. The MEMS package further includes an anti-stiction layer disposed under the moveable mass. The anti-stiction layer is made of metal and has a rough top surface.
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公开(公告)号：US20180148320A1
公开(公告)日：2018-05-31
申请号：US15694176
申请日：2017-09-01
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chih-Chien Yang , Ming-Lun Shih , Ren-Dou Lee , Jen-Hao Liu
CPC classification number: B81B7/0041 , B81B2201/0264 , B81B2207/097 , B81C1/00293 , B81C2203/0145 , B81C2203/036 , G01L9/0048 , G01L9/0072 , G01L9/008
Abstract: A multi-layer sealing film for high seal yield is provided. In some embodiments, a substrate comprises a vent opening extending through the substrate, from an upper side of the substrate to a lower side of the substrate. The upper side of the substrate has a first pressure, and the lower side of the substrate has a second pressure different than the first pressure. The multi-layer sealing film covers and seals the vent opening to prevent the first pressure from equalizing with the second pressure through the vent opening. Further, the multi-layer sealing film comprises a pair of metal layers and a barrier layer sandwiched between metal layers. Also provided is a microelectromechanical systems (MEMS) package comprising the multilayer sealing film, and a method for manufacturing the multi-layer sealing film.
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Patent Agency Ranking
6.发明授权公开(公告)号：US09230918B1
公开(公告)日：2016-01-05
申请号：US14322495
申请日：2014-07-02
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Ting-Ying Chien , I-Shi Wang , Jen-Hao Liu , Ren-Dou Lee
IPC: H01L23/544 , H01L23/00
CPC classification number: H01L23/544 , H01L24/32 , H01L24/83 , H01L24/94 , H01L2223/54426 , H01L2224/291 , H01L2224/32145 , H01L2224/83139 , H01L2224/83141 , H01L2224/94 , H01L2224/83 , H01L2924/014
Abstract: A semiconductor package structure includes a first wafer and a second wafer. The first wafer has a concave portion. The concave portion has a bottom surface and at least one sidewall adjacent to the bottom surface. An obtuse angle is formed between the bottom surface and the sidewall. The second wafer is disposed on the first wafer and has a protruding portion. When the protruding portion enters an opening of the concave portion, the protruding portion slides along the sidewall to the bottom surface, such that the protruding portion is coupled to the concave portion.
Abstract translation: 半导体封装结构包括第一晶片和第二晶片。 第一晶片具有凹部。 凹部具有底表面和邻近底表面的至少一个侧壁。 在底面和侧壁之间形成钝角。 第二晶片设置在第一晶片上并具有突出部分。 当突出部分进入凹部的开口时，突出部分沿着侧壁滑动到底面，使得突出部分联接到凹部。
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公开(公告)号：US09725312B1
公开(公告)日：2017-08-08
申请号：US15016527
申请日：2016-02-05
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chien-Ning Hsin , I-Shi Wang , Jen-Hao Liu , Chih-Hang Chang
CPC classification number: B81C1/00357 , B81C1/00269 , B81C2203/036 , B81C2203/037 , H01L21/02334 , H01L21/02337 , H01L21/2007 , H01L21/3105
Abstract: A method for fusion bonding a pair of substrates together with silane preconditioning is provided. A surface of a first oxide layer or a surface of a second oxide layer is preconditioned with silane. The first and second oxide layers are respectively arranged on first and second semiconductor substrates. Water is applied to the surface of the first or second oxide layer. The surfaces of the first and second oxide layers are brought in direct contact. The first and second oxide layers are annealed. A method for manufacturing a microelectromechanical systems (MEMS) package using the fusion bonding is also provided.
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公开(公告)号：US11192778B2
公开(公告)日：2021-12-07
申请号：US16927223
申请日：2020-07-13
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yu-Jui Chen , I-Shi Wang , Ren-Dou Lee , Jen-Hao Liu
Abstract: A method includes: providing a first substrate on which a plurality of first semiconductor devices is formed; providing a second substrate on which a plurality of second semiconductor devices is formed; and coupling the first and second substrates by contacting respective dummy pads of the first and second substrates, wherein at least one of the dummy pads of the first and second substrates comprises plural peaks and valleys.
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公开(公告)号：US10710872B2
公开(公告)日：2020-07-14
申请号：US15833072
申请日：2017-12-06
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yu-Jui Chen , I-Shi Wang , Ren-Dou Lee , Jen-Hao Liu
Abstract: A method includes: providing a first substrate on which a plurality of first semiconductor devices is formed; providing a second substrate on which a plurality of second semiconductor devices is formed; and coupling the first and second substrates by contacting respective dummy pads of the first and second substrates, wherein at least one of the dummy pads of the first and second substrates comprises plural peaks and valleys.
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公开(公告)号：US20190092622A1
公开(公告)日：2019-03-28
申请号：US16202444
申请日：2018-11-28
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chih-Chien Yang , Ming-Lun Shih , Ren-Dou Lee , Jen-Hao Liu
CPC classification number: B81B7/0041 , B81B2201/0264 , B81B2207/012 , B81B2207/097 , B81C1/00293 , B81C2203/0145 , B81C2203/036 , B81C2203/0735 , B81C2203/0771 , G01L9/0048 , G01L9/0072 , G01L9/008
Abstract: A multi-layer sealing film for high seal yield is provided. In some embodiments, a substrate comprises a vent opening extending through the substrate, from an upper side of the substrate to a lower side of the substrate. The upper side of the substrate has a first pressure, and the lower side of the substrate has a second pressure different than the first pressure. The multi-layer sealing film covers and seals the vent opening to prevent the first pressure from equalizing with the second pressure through the vent opening. Further, the multi-layer sealing film comprises a pair of metal layers and a barrier layer sandwiched between metal layers. Also provided is a microelectromechanical systems (MEMS) package comprising the multilayer sealing film, and a method for manufacturing the multi-layer sealing film.
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