公开(公告)号：US20240371650A1

公开(公告)日：2024-11-07

申请号：US18775605

申请日：2024-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Li Lin ,  Chih-Teng Liao ,  Jui Fu Hsieh ,  Chih Hsuan Cheng ,  Tzu-Chan Weng

IPC: H01L21/3065 ,  H01J37/32 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming a gate layer over the fin; and patterning the gate layer in a plasma etching tool using a plasma etching process to form a gate over the fin, where patterning the gate layer includes: turning on and off a top radio frequency (RF) source of the plasma etching tool alternately during the plasma etching process; and turning on and off a bottom RF source of the plasma etching tool alternately during the plasma etching process, where there is a timing offset between first time instants when the top RF source is turned on and respective second time instants when the bottom RF source is turned on.

公开(公告)号：US11532481B2

公开(公告)日：2022-12-20

申请号：US16916465

申请日：2020-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Li Lin ,  Chih-Teng Liao ,  Jui Fu Hsieh ,  Chih Hsuan Cheng ,  Tzu-Chan Weng

IPC: H01L21/3065 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01J37/32

Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming a gate layer over the fin; and patterning the gate layer in a plasma etching tool using a plasma etching process to form a gate over the fin, where patterning the gate layer includes: turning on and off a top radio frequency (RF) source of the plasma etching tool alternately during the plasma etching process; and turning on and off a bottom RF source of the plasma etching tool alternately during the plasma etching process, where there is a timing offset between first time instants when the top RF source is turned on and respective second time instants when the bottom RF source is turned on.

公开(公告)号：US20220367196A1

公开(公告)日：2022-11-17

申请号：US17814607

申请日：2022-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Li Lin ,  Chih-Teng Liao ,  Jui Fu Hsieh ,  Chih Hsuan Cheng ,  Tzu-Chan Weng

IPC: H01L21/3065 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01J37/32

Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming a gate layer over the fin; and patterning the gate layer in a plasma etching tool using a plasma etching process to form a gate over the fin, where patterning the gate layer includes: turning on and off a top radio frequency (RF) source of the plasma etching tool alternately during the plasma etching process; and turning on and off a bottom RF source of the plasma etching tool alternately during the plasma etching process, where there is a timing offset between first time instants when the top RF source is turned on and respective second time instants when the bottom RF source is turned on.

公开(公告)号：US11430893B2

公开(公告)日：2022-08-30

申请号：US16926521

申请日：2020-07-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yan-Ting Shen ,  Chia-Chi Yu ,  Chih-Teng Liao ,  Yu-Li Lin ,  Chih Hsuan Cheng ,  Tzu-Chan Weng

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66

Abstract: A semiconductor device includes a fin structure protruding from an isolation insulating layer disposed over a substrate and having a channel region, a source/drain region disposed over the substrate, a gate dielectric layer disposed on the channel region, and a gate electrode layer disposed on the gate dielectric layer. The gate electrode includes a lower portion below a level of a top of the channel region and above an upper surface of the isolation insulating layer, and a width of the lower portion is not constant.

公开(公告)号：US20210407812A1

公开(公告)日：2021-12-30

申请号：US16916465

申请日：2020-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Li Lin ,  Chih-Teng Liao ,  Jui Fu Hsieh ,  Chih Hsuan Cheng ,  Tzu-Chan Weng

IPC: H01L21/3065 ,  H01L21/8234 ,  H01J37/32 ,  H01L29/78 ,  H01L29/66

Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming a gate layer over the fin; and patterning the gate layer in a plasma etching tool using a plasma etching process to form a gate over the fin, where patterning the gate layer includes: turning on and off a top radio frequency (RF) source of the plasma etching tool alternately during the plasma etching process; and turning on and off a bottom RF source of the plasma etching tool alternately during the plasma etching process, where there is a timing offset between first time instants when the top RF source is turned on and respective second time instants when the bottom RF source is turned on.

公开(公告)号：US12125707B2

公开(公告)日：2024-10-22

申请号：US17814607

申请日：2022-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Li Lin ,  Chih-Teng Liao ,  Jui Fu Hsieh ,  Chih Hsuan Cheng ,  Tzu-Chan Weng

IPC: H01L21/3065 ,  H01J37/32 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/3065 ,  H01J37/32174 ,  H01L21/823431 ,  H01L29/6681 ,  H01L29/785

Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming a gate layer over the fin; and patterning the gate layer in a plasma etching tool using a plasma etching process to form a gate over the fin, where patterning the gate layer includes: turning on and off a top radio frequency (RF) source of the plasma etching tool alternately during the plasma etching process; and turning on and off a bottom RF source of the plasma etching tool alternately during the plasma etching process, where there is a timing offset between first time instants when the top RF source is turned on and respective second time instants when the bottom RF source is turned on.

公开(公告)号：US20220406913A1

公开(公告)日：2022-12-22

申请号：US17824491

申请日：2022-05-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiu-Ling Chen ,  Chih-Teng Liao ,  Jen-Chih Hsueh ,  Chen-Wei Pan ,  Yu-Li Lin

IPC: H01L29/423 ,  H01L27/092 ,  H01L29/78 ,  H01L29/49 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/66

Abstract: Embodiments include methods and devices which utilize dummy gate profiling to provide a profile of a dummy gate which has narrowing in the dummy gate. The narrowing causes a neck in the dummy gate. When the dummy gate is replaced in a gate replacement process, the necking provides control of an etch-back process. Space is provided between the replacement gate and a subsequently formed self-aligned contact.

公开(公告)号：US11282944B2

公开(公告)日：2022-03-22

申请号：US16945557

申请日：2020-07-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Chi Yu ,  Jui Fu Hseih ,  Yu-Li Lin ,  Chih-Teng Liao ,  Yi-Jen Chen

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L21/311 ,  H01L29/08 ,  H01L29/06

Abstract: In a method, a first dielectric layer is formed over semiconductor fins, a second dielectric layer is formed over the first dielectric layer, the second dielectric layer is recessed below a top of each of the semiconductor fins, a third dielectric layer is formed over the recessed second dielectric layer, and the third dielectric layer is recessed below the top of the semiconductor fin, thereby forming a wall fin. The wall fin includes the recessed third dielectric layer and the recessed second dielectric layer disposed over the recessed third dielectric layer. The first dielectric layer is recessed below a top of the wall fin, a fin liner layer is formed, the fin liner layer is recessed and the semiconductor fins are recessed, and source/drain epitaxial layers are formed over the recessed semiconductor fins, respectively. The source/drain epitaxial layers are separated by the wall fin from each other.