公开(公告)号：US11430893B2

公开(公告)日：2022-08-30

申请号：US16926521

申请日：2020-07-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yan-Ting Shen ,  Chia-Chi Yu ,  Chih-Teng Liao ,  Yu-Li Lin ,  Chih Hsuan Cheng ,  Tzu-Chan Weng

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66

Abstract: A semiconductor device includes a fin structure protruding from an isolation insulating layer disposed over a substrate and having a channel region, a source/drain region disposed over the substrate, a gate dielectric layer disposed on the channel region, and a gate electrode layer disposed on the gate dielectric layer. The gate electrode includes a lower portion below a level of a top of the channel region and above an upper surface of the isolation insulating layer, and a width of the lower portion is not constant.

公开(公告)号：US20210407812A1

公开(公告)日：2021-12-30

申请号：US16916465

申请日：2020-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Li Lin ,  Chih-Teng Liao ,  Jui Fu Hsieh ,  Chih Hsuan Cheng ,  Tzu-Chan Weng

IPC: H01L21/3065 ,  H01L21/8234 ,  H01J37/32 ,  H01L29/78 ,  H01L29/66

Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming a gate layer over the fin; and patterning the gate layer in a plasma etching tool using a plasma etching process to form a gate over the fin, where patterning the gate layer includes: turning on and off a top radio frequency (RF) source of the plasma etching tool alternately during the plasma etching process; and turning on and off a bottom RF source of the plasma etching tool alternately during the plasma etching process, where there is a timing offset between first time instants when the top RF source is turned on and respective second time instants when the bottom RF source is turned on.

公开(公告)号：US12125707B2

公开(公告)日：2024-10-22

申请号：US17814607

申请日：2022-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Li Lin ,  Chih-Teng Liao ,  Jui Fu Hsieh ,  Chih Hsuan Cheng ,  Tzu-Chan Weng

IPC: H01L21/3065 ,  H01J37/32 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/3065 ,  H01J37/32174 ,  H01L21/823431 ,  H01L29/6681 ,  H01L29/785

Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming a gate layer over the fin; and patterning the gate layer in a plasma etching tool using a plasma etching process to form a gate over the fin, where patterning the gate layer includes: turning on and off a top radio frequency (RF) source of the plasma etching tool alternately during the plasma etching process; and turning on and off a bottom RF source of the plasma etching tool alternately during the plasma etching process, where there is a timing offset between first time instants when the top RF source is turned on and respective second time instants when the bottom RF source is turned on.

公开(公告)号：US20230207665A1

公开(公告)日：2023-06-29

申请号：US18178660

申请日：2023-03-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Teng Liao ,  Chia-Cheng Tai ,  Tzu-Chan Weng ,  Yi-Wei Chiu ,  Chih Hsuan Cheng

IPC: H01L29/66 ,  H01L21/3213 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/423

CPC classification number: H01L29/66545 ,  H01L21/32136 ,  H01L21/32137 ,  H01L21/823431 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/42316 ,  H01L29/66795

Abstract: A method includes forming a semiconductor fin extending a first height above a substrate, forming a dummy dielectric material over the semiconductor fin and over the substrate, forming a dummy gate material over the dummy dielectric material, the dummy gate material extending a second height above the substrate, etching the dummy gate material using multiple etching processes to form a dummy gate stack, wherein each etching process of the multiple etching processes is a different etching process, wherein the dummy gate stack has a first width at the first height, and wherein the dummy gate stack has a second width at the second height that is different from the first width.

公开(公告)号：US12300741B2

公开(公告)日：2025-05-13

申请号：US18178660

申请日：2023-03-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Teng Liao ,  Chia-Cheng Tai ,  Tzu-Chan Weng ,  Yi-Wei Chiu ,  Chih Hsuan Cheng

IPC: H01L29/66 ,  H01L21/3213 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/78

Abstract: A method includes forming a semiconductor fin extending a first height above a substrate, forming a dummy dielectric material over the semiconductor fin and over the substrate, forming a dummy gate material over the dummy dielectric material, the dummy gate material extending a second height above the substrate, etching the dummy gate material using multiple etching processes to form a dummy gate stack, wherein each etching process of the multiple etching processes is a different etching process, wherein the dummy gate stack has a first width at the first height, and wherein the dummy gate stack has a second width at the second height that is different from the first width.

公开(公告)号：US10510875B2

公开(公告)日：2019-12-17

申请号：US16000689

申请日：2018-06-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Teng Liao ,  Chih-Shan Chen ,  Yi-Wei Chiu ,  Chih Hsuan Cheng ,  Tzu-Chan Weng

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/324 ,  H01L29/78 ,  H01L29/417 ,  H01L29/08 ,  H01L21/306 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06

Abstract: A method includes forming a fin structure on the substrate, wherein the fin structure includes a first fin active region; a second fin active region; and an isolation feature separating the first and second fin active regions; forming a first gate stack on the first fin active region and a second gate stack on the second fin active region; performing a first recessing process to a first source/drain region of the first fin active region by a first dry etch; performing a first epitaxial growth to form a first source/drain feature on the first source/drain region; performing a fin sidewall pull back (FSWPB) process to remove a dielectric layer on the second fin active region; and performing a second epitaxial growth to form a second source/drain feature on a second source/drain region of the second fin active region.

公开(公告)号：US20190035908A1

公开(公告)日：2019-01-31

申请号：US16000689

申请日：2018-06-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Teng Liao ,  Chih-Shan Chen ,  Yi-Wei Chiu ,  Chih Hsuan Cheng ,  Tzu-Chan Weng

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/324 ,  H01L21/306 ,  H01L29/78 ,  H01L29/417 ,  H01L29/08

Abstract: A method includes forming a fin structure on the substrate, wherein the fin structure includes a first fin active region; a second fin active region; and an isolation feature separating the first and second fin active regions; forming a first gate stack on the first fin active region and a second gate stack on the second fin active region; performing a first recessing process to a first source/drain region of the first fin active region by a first dry etch; performing a first epitaxial growth to form a first source/drain feature on the first source/drain region; performing a fin sidewall pull back (FSWPB) process to remove a dielectric layer on the second fin active region; and performing a second epitaxial growth to form a second source/drain feature on a second source/drain region of the second fin active region.

公开(公告)号：US20240371650A1

公开(公告)日：2024-11-07

申请号：US18775605

申请日：2024-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Li Lin ,  Chih-Teng Liao ,  Jui Fu Hsieh ,  Chih Hsuan Cheng ,  Tzu-Chan Weng

IPC: H01L21/3065 ,  H01J37/32 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming a gate layer over the fin; and patterning the gate layer in a plasma etching tool using a plasma etching process to form a gate over the fin, where patterning the gate layer includes: turning on and off a top radio frequency (RF) source of the plasma etching tool alternately during the plasma etching process; and turning on and off a bottom RF source of the plasma etching tool alternately during the plasma etching process, where there is a timing offset between first time instants when the top RF source is turned on and respective second time instants when the bottom RF source is turned on.

公开(公告)号：US20230142157A1

公开(公告)日：2023-05-11

申请号：US18149267

申请日：2023-01-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Teng Liao ,  Chih-Shan Chen ,  Yi-Wei Chiu ,  Chih Hsuan Cheng ,  Tzu-Chan Weng

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/324 ,  H01L29/78 ,  H01L29/417 ,  H01L29/08 ,  H01L21/306 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/06

CPC classification number: H01L29/6681 ,  H01L21/823431 ,  H01L21/823418 ,  H01L21/324 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/41791 ,  H01L29/0847 ,  H01L21/30625 ,  H01L27/092 ,  H01L21/823821 ,  H01L29/0653 ,  H01L29/66545 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/845

Abstract: A semiconductor device includes first and second fin active regions extruding from a substrate, where the first and second fin active regions are separated by an isolation feature. The semiconductor includes a first gate stack disposed on the first fin active region and a second gate stack disposed on the second fin active region. The semiconductor device includes first source/drain features formed on the first fin active region, second source/drain features formed on the second fin active region, and a dielectric layer disposed along sidewalls of the first fin active region but not along sidewalls of the second fin active region. The first source/drain features extend vertically into the first fin active region at a first depth, the second source/drain features extend vertically into the second fin active region at a second depth, and the first depth is greater than the second depth.

公开(公告)号：US11545562B2

公开(公告)日：2023-01-03

申请号：US16715347

申请日：2019-12-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Teng Liao ,  Chih-Shan Chen ,  Yi-Wei Chiu ,  Chih Hsuan Cheng ,  Tzu-Chan Weng

IPC: H01L21/70 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/324 ,  H01L29/78 ,  H01L29/417 ,  H01L29/08 ,  H01L21/306 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L21/84

Abstract: A method includes forming a fin structure on the substrate, wherein the fin structure includes a first fin active region; a second fin active region; and an isolation feature separating the first and second fin active regions; forming a first gate stack on the first fin active region and a second gate stack on the second fin active region; performing a first recessing process to a first source/drain region of the first fin active region by a first dry etch; performing a first epitaxial growth to form a first source/drain feature on the first source/drain region; performing a fin sidewall pull back (FSWPB) process to remove a dielectric layer on the second fin active region; and performing a second epitaxial growth to form a second source/drain feature on a second source/drain region of the second fin active region.